Abstract:
In a keyboard, an elastic diaphragm switch array and logic, including strobe and rollover protection. The switch includes a diaphragm, a separator, and a switch card. The diaphragm comprises a gold plated continuous sheet of thin spring material and serves as a ground or voltage plane. The switch card has a gold plated pie pattern or switch array at each key location, with generally as many pie sections as there are bits in the code to be produced. Each pie section is wired directly by double sided wiring and through-holes in the switch card to the appropriate output code pin. No decoding or encoding logic is required to produce the code. Strobe logic is provided for assuring that all pie sections have made contact with the diaphragm and rollover protection logic is provided for assuring that only one key is depressed. A key button is provided for pressing the diaphragm through the separator to make contact with the switch card pie pattern.
Abstract:
A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.
Abstract:
In a keyboard, an elastic diaphragm switch array providing mechanical strobe and rollover protection, and/or a serial signal output. The switch includes a diaphragm, a separator, and a switch card. The diaphragm comprises a gold-plated continuous sheet of thin spring material and serves as a ground or voltage plane or voltage adder. The switch card has a conductive switch array (or pie section pattern) at each key location and may have twice as many pie sections as there are bits in the code to be produced or voltage transitions desired in the output, with additional service pie sections as desired. Each pie section is wired directly by double-sided wiring and through-holes in the switch card to the appropriate output code pin, a positive or negative voltage source, or other connection. A key button and distributor is provided for pressing the diaphragm smoothly through the separator to make contact with the corresponding switch card pie section. In each pie pattern, at least one of the pie sections is offset from the center of contact of the key button such that, as the key button is actuated and the diaphragm pressed through the separator, that pie section makes contact at a different point in time to provide a serial code signal output, or provide such service functions as strobe, rollover protection, switch battery power, or the like.
Abstract:
A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.