公开(公告)号：MY127563A

公开(公告)日：2006-12-29

申请号：MYPI20020088

申请日：2002-01-11

Applicant: IBM

Inventor： BALLANTINE ARNE W ,  GROVES ROBERT A ,  LUND JENNIFER L ,  NAKOS JAMES S ,  RICE MICHAEL B ,  STAMPER ANTHONY K

IPC: H01L21/768 ,  H01L29/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/822 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A METHOD AND STURCTURE THAT PROVIDES A BATTERY (420) WITHIN AN INTEGRATED CIRCUIT (400) FOR PROVIDING VOLTAGE TO LOW-CURRENT ELECTRONIC DEVICES (900) THAT EXIST WITHIN THE INTERGRATED CIRCUIT. THE METHOD INCLUDES FRONT-END-OF-LINE (FEOL) PROCESSING FOR GENERATING A LAYER OF ELECTRONIC DEVICES ON A SEMICONDUCTOR WAFER (402), FOLLOWED BY BACK-END-OF-LINE(BEOL) INTEGRATION FOR WIRES THE BEOL INTEGRATION INCLUDES FORMING A MULTILAYERED STRUCTURE OF WIRING LEVELS ON THE LAYER OF ELECTORINC DEVICES. EACH WIRING LEVEL INCLUDES CONDUCTIVE METALLIZATION (E.G., METAL-PLATED VIAS CONDUCTIVE WIRING LINES, ETC) EMBEDDED IN INSULATIVE MATERIAL. THE BATTERY IS FORMED DURING BEOL INTEGRATION WITHIN ONE OR MORE WIRING LEVELS, AND THE CONDUCTIVE METALLIZATION (432,434,442,444)(E.G.,METAL-PALTED VIAS,CONDUCTIVE WIRING LINES, ETC.)EMBEDDED IN INSULATIVE MATERIAL.THE BATTERY IS FORMED DURING BEOL INTEGRATION WITHIN ONE OR MORE WIRING LEVELS,AND THE CONDUCTIVE METALLIZATION CONDUCTIVELY COUPLE POSITIVE (424) AND NEGATIVE (422) TERMINALS OF THE BATERRY TO THE ELECTRONIC DEVICES.THE BATERRY MAY HAVE SEVERAL DIFFERENT TOPOLOGIES RELATIVE TO THE STRUCTURAL AND GEOMETRICAL RELATIONSHIPS AMONG THE BATERRY ELECTRODES AND ELECTROLYTE.MULTIPLE BATTERIES MAY BE FORMED WITHIN ONE OR MORE WIRING LEVELS,AND MAY BE CONDUCTIVELY COUPLE TO THE ELECTRONIC DEVICES.THE MULTIPLE BATERIES MAY BE CONNECTED IN SERIES OR IN PARALLEL.(FIG.1)