公开(公告)号：CA1176377A

公开(公告)日：1984-10-16

申请号：CA400593

申请日：1982-04-07

Applicant: IBM

Inventor： BULLIONS ROBERT J III ,  CURLEE THOMAS O III ,  GUM PETER H ,  MCGILVRAY BRUCE L ,  RICHARDSON ETHEL L

IPC: G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F12/10 ,  G11C9/00

Abstract: PO9-80-005 The described embodiment provides translation look-aside buffer (TLB) hardware in a CP that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Each TLB entry contains hardware which indicates whether the address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request if it is a real or virtual address. Intermediate translations for a double-level translation are inhibited from being loaded into the TLB. Guest entries are purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces its hardware adder translation hard ware to translate each accelerated preferred guest request, since it requires only a single level translation. A nonaccelerated guest request is instead translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.