公开(公告)号：CA1176377A

公开(公告)日：1984-10-16

申请号：CA400593

申请日：1982-04-07

Applicant: IBM

Inventor： BULLIONS ROBERT J III ,  CURLEE THOMAS O III ,  GUM PETER H ,  MCGILVRAY BRUCE L ,  RICHARDSON ETHEL L

IPC: G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F12/10 ,  G11C9/00

Abstract: PO9-80-005 The described embodiment provides translation look-aside buffer (TLB) hardware in a CP that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Each TLB entry contains hardware which indicates whether the address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request if it is a real or virtual address. Intermediate translations for a double-level translation are inhibited from being loaded into the TLB. Guest entries are purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces its hardware adder translation hard ware to translate each accelerated preferred guest request, since it requires only a single level translation. A nonaccelerated guest request is instead translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

公开(公告)号：DE3483120D1

公开(公告)日：1990-10-11

申请号：DE3483120

申请日：1984-06-20

Applicant: IBM

Inventor： GUM PETER H ,  SMITH RONALD M ,  LEVIN ARTHUR L ,  WILSON JOHN H

IPC: G06F11/28 ,  G06F11/36 ,  G06F15/16 ,  G06F15/177 ,  G06F11/00

Abstract: The method provides a separate trace table (TT) for each CPU in an MP (multiprocessor) to avoid inter-CPU interference in making trace table entries (16) for explicit and implicit tracing instructions enabled by flag bits (E, A, B) in a control register (CR). Explicit tracing entries are made for an enabled explicit tracing (TR) instruction (11). Implicit tracing entries are made for predetermined instructions (when enabled for tracing) which do not have tracing as their primary purpose. A storage operand (12) of the trace instruction (11) contains a disablement field (T) and optionally may contain an enablement-controlling class field (4...7) to improve the integrity of traceable programs. A time stamp and a range of general register (R1...R3) contents is provided in each trace table entry for a tracing instruction. The time stamp enables all trace tables in an MP system to be later merged into a single trace table whenever required.

公开(公告)号：CA2068796A1

公开(公告)日：1993-03-01

申请号：CA2068796

申请日：1992-05-15

Applicant: IBM

Inventor： CHOU NORMAN C ,  GUM PETER H ,  HOUGH ROGER E ,  KIM MOON J ,  MAZUROWSKI JAMES C ,  MCCAULEY DONALD W ,  SCALZI CASPER A ,  SCANLON JOHN F ,  WYMAN LESLIE W

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16

Abstract: P09-91-035 CPU EXPANSIVE GRADATION OF I/O INTERRUPTION SUBCLASS RECOGNITION A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

公开(公告)号：CA1182575A

公开(公告)日：1985-02-12

申请号：CA424283

申请日：1983-03-23

Applicant: IBM

Inventor： BEAN GEORGE H ,  GUM PETER H

IPC: G06F9/46 ,  G06F9/455 ,  G06F9/48

Abstract: The embodiment switches an address in a prefix register in a CPU of a MP or UP data processing system from one PSA (program save area) to another PSA. The prefix address switching changes the control of the CPU from a preferred guest SCP (system control program) to a host SCP. This switching is done by hardware/ microcode means which is not controllable by user instructions executable on the CPU. This manner of CPU control switching obtains for a preferred guest SCP (such as MVS/370) operating in relation to a host SCP (such as VM/370) nearly the efficiency of standalone execution on the CPU by a preferred guest SCP that is the same as a standalone version of the guest SCP.

公开(公告)号：DE3479454D1

公开(公告)日：1989-09-21

申请号：DE3479454

申请日：1984-11-14

Applicant: IBM

Inventor： GUM PETER H ,  HOUGH ROGER E ,  TALLMAN PETER H ,  CURLEE THOMAS O

IPC: G06F9/455 ,  G06F9/48 ,  G06F12/10 ,  G06F9/46 ,  G06F9/44

公开(公告)号：CA1213986A

公开(公告)日：1986-11-12

申请号：CA465434

申请日：1984-10-15

Applicant: IBM

Inventor： GUM PETER H ,  HOUGH ROGER E ,  TALLMAN PETER H ,  CURLEE THOMAS O III

IPC: G06F9/455 ,  G06F9/48 ,  G06F12/10 ,  G06F9/44

Abstract: The disclosed embodiments enable address translations for a virtual machine in the TLB of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided lo allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.