公开(公告)号：CA1176377A

公开(公告)日：1984-10-16

申请号：CA400593

申请日：1982-04-07

Applicant: IBM

Inventor： BULLIONS ROBERT J III ,  CURLEE THOMAS O III ,  GUM PETER H ,  MCGILVRAY BRUCE L ,  RICHARDSON ETHEL L

IPC: G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F12/10 ,  G11C9/00

Abstract: PO9-80-005 The described embodiment provides translation look-aside buffer (TLB) hardware in a CP that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Each TLB entry contains hardware which indicates whether the address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request if it is a real or virtual address. Intermediate translations for a double-level translation are inhibited from being loaded into the TLB. Guest entries are purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces its hardware adder translation hard ware to translate each accelerated preferred guest request, since it requires only a single level translation. A nonaccelerated guest request is instead translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

公开(公告)号：CA1213986A

公开(公告)日：1986-11-12

申请号：CA465434

申请日：1984-10-15

Applicant: IBM

Inventor： GUM PETER H ,  HOUGH ROGER E ,  TALLMAN PETER H ,  CURLEE THOMAS O III

IPC: G06F9/455 ,  G06F9/48 ,  G06F12/10 ,  G06F9/44

Abstract: The disclosed embodiments enable address translations for a virtual machine in the TLB of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided lo allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.