公开(公告)号：JPH0714891A

公开(公告)日：1995-01-17

申请号：JP8145894

申请日：1994-04-20

Applicant: IBM

Inventor： MOORISU ANSHIERU ,  ANSONII POORU INGURAHAMU ,  CHIYAARUZU ROBAATO RAMU ,  MAIKERU DEBITSUDO ROUERU ,  BOOYA RISUTA MARUKOBITSUCHI ,  UORUFUGANGU MAIYAA ,  RICHIYAADO JIERARUDO MAAFUII ,  MAAKU BINSENTO PIERUSON ,  TAMAA AREEN PAWAAZU ,  TEIMOSHII SHIYOUN RENII ,  SUKOTSUTO DEBITSUDO REINORUZU ,  BAAGATSUTO GAREBU SAMAKIA ,  UEIN RATSUSERU SUTOA

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01R13/02

Abstract: PURPOSE: To enable an integrated circuit chip to be checked at a high speed with renewability, low cost and high throughput, by providing a chip checking fixture system with a contact corresponding to a contact of a semiconductor chip. CONSTITUTION: An integrated circuit chip 31 to be checked has a plurality of I/Os, a power supply and a ground contact. A chip checking fixture system includes a burn-in board 11 with a dendrite contact 13 corresponding to a contact of the integrated circuit chip 31, a heating device and a pressing jig. By using the system, the integrated circuit chip 31 is placed on the burn-in board 11, pressed, brought into electrical contact with the dendrite contact 13, and checked electrically, logically and thermally. Thereby, the position of the chip is easily adjusted, the chip is easily attached and detached to and from the system before and after the checking respectively, and is checked at high speed, renewability, low cost and high throughput.

公开(公告)号：JPH06252226A

公开(公告)日：1994-09-09

申请号：JP1328194

申请日：1994-02-07

Applicant: IBM

Inventor： ANIRUKUMARU CHINUPURASADO BATS ,  REO REIMONDO BUDA ,  ROBAATO DAGURASU EDOWAAZU ,  POORU JIYOOZEFU HAATO ,  ANSONII POORU INGURAHAMU ,  BUOYA RISUTA MARUKOBUICHI ,  JIYAINARU AABEDEIIN MOTSURA ,  RICHIYAADO JIERARUDO MAAFUII ,  JIYOOJI SAKUSENMAIYAA JIYUNIA ,  JIYOOJI FUREDERITSUKU UOOKAA ,  BETSUTO JIEI HOUEEREN ,  RICHIYAADO SUCHIYUAATO ZARU

IPC: G01R31/28 ,  H01L21/60 ,  H01L21/66

Abstract: PURPOSE: To provide simulated site test and actual site test for integrated circuit chip by providing a contact corresponding to the contact of semiconductor chip and defining the contact of carrier as a chip carrier having a dendrite surface. CONSTITUTION: A semiconductor circuit chip is placed on a board or a test jig while facing a connector on the board. The board or jig has the dendrite in structure including a conductive pad or substrate, smooth Pd lower layer and upper layer such as a pole-shaped Pd layer on the connecting plane, contact or pad of chip. Then, the chip and the board are contacted and compressing force is applied to the chip and the board. Afterwards, various logic tests and memory tests are performed to the integrated circuit chip while applying power between the input and the ground, and unsuccessful chip is discarded but the successful chip is bonded to the board between the bonding pad and the dendritic surface.

公开(公告)号：JPH04234157A

公开(公告)日：1992-08-21

申请号：JP21422291

申请日：1991-08-01

Applicant: IBM

Inventor： MORISU ANSHIERU ,  HOSE AGUSUCHIN BAABOSA ,  ERITSUKU POORU DEITSUBURU ,  JIYOSEFU FUNARI ,  JIYON SUTEIIBUN KURESUGE ,  CHIYAARUZU ROBAATO RAMU ,  RICHIYAADO JIERARUDO MAAFUII ,  SUKOTSUTO DEBITSUDO RENORUZU ,  BAAGATSUTO GAAREBU SAMAKIA ,  TAAMAA ARAN SHIYORUTSU ,  UEIN RATSUSERU SUTOORU JIYUNIA

IPC: H01L23/36 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K1/18

Abstract: PURPOSE: To provide an ultra-compact electronic package that is suited for a high memory capacity and a high memory density, and to use a double-sided surface-mount technology assembly additionally. CONSTITUTION: A package 1 contains a plurality of IC memory chips 11 that are adhered to a circuited flexible tape substrate 21, and the circuited flexible tape substrate 21 is adhered to a printed circuit board 31 later. The circuited flexible tape substrate 21 is extended outward from the printed circuit board 31 and has a plurality of IC memory chips 11 mounted to an I/O pad on it. Each IC memory chip 11 is in contact with a heat sink means 41 on a surface that is opposite to the flexible tape substrate 21. The flexible tape substrate 21 and the heat sink means 41 are joined to the printed circuit board 31.