公开(公告)号：JPH10321807A

公开(公告)日：1998-12-04

申请号：JP12094798

申请日：1998-04-30

Applicant: IBM

Inventor： FEI D BAKER ,  JEFFREY S BROWN ,  ROBERT J GAUZAR ,  STEPHEN J HORMES ,  ROBERT K LADY ,  EDWARD J NOWACK ,  VOLDMAN STEVEN H

IPC: H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To improve the latch-up resistance of a CMOS device by forming implants on the edges of an N well and/or a P well by using a hybrid resist and, at the same time, to improve the device density of the CMOS device by promoting the scaling of the device. SOLUTION: A wafer section 2100 can be completed by an appropriate manufacturing method, for example, by forming a device gate, a contact diffusion area, etc. In the wafer section 2100, in addition, N and P contact diffusion areas are formed. In these contact diffusion areas, implants are usually formed on the surface of silicon which is not masked with a polysilicon gate. Therefore, a method and a structure for reducing the latch-up of a CMOS device by forming N and/or P edge implants on the edges of a P-well, N-well, and/or a double well are obtained.