公开(公告)号：JPH1174196A

公开(公告)日：1999-03-16

申请号：JP19275998

申请日：1998-07-08

Applicant: IBM

Inventor： JEFFREY S BROWN ,  JAMES S DUNE ,  STEPHEN J HORMES ,  KAKU K HYUIN ,  LEIDY ROBERT K ,  PAUL W PASTELL

IPC: H01L29/78 ,  G03F7/095 ,  G03F7/38 ,  H01L21/027 ,  H01L21/265 ,  H01L21/311 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To enable junctions of a gate/source and a gate/drain to be enhanced in control in doping by a method, wherein a side wall spacer trough is demarcated by the use of a hybrid resist. SOLUTION: A wafer is prepared, and a hybrid resist layer is attached to the wafer, exposed to light through a mask, and developed (302 to 308) for the formation of a sidewall spacer. A hard mask is etched through a spacer (301), a uniform exposure process and a development process are carried out (312), a gate matter is etched through the residual hard mask (314), and a sidewall spacer trough is formed. Then, the exposed hard mask and a negative-type hybrid resist are removed (316 and 313), and a gate edge implant is formed (320). Then, a sidewall oxide and a nitride stopper are attached (322), an excess sidewall spacer matter and an excess gate matter are removed (326 and 328), and are injected (330) to a source and a drain region.

公开(公告)号：JPH11330384A

公开(公告)日：1999-11-30

申请号：JP20197998

申请日：1998-07-16

Applicant: IBM

Inventor： JEFFREY S BROWN ,  JAMES S DUNE ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  LEIDY ROBERT K ,  STEPHEN H BALDEMAN

IPC: G03F7/26 ,  G03F7/40 ,  H01L21/027 ,  H01L21/336 ,  H01L27/08 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enhance a CMOS device in latch up resistance, by a method wherein a side wall spacer/trough region is demarcated and formed by the use of hybrid photoresist which shows a positive-type, a negative type and an intermediate-type reaction to exposure light. SOLUTION: A gate oxide layer 2404 and a gate material layer 2406 are successively deposited on a wafer 2500, and side wall spacer troughs 2801 and 2802 are provided to the gate oxide layer 2404 and the gate material layer 2406 by the use of hybrid photoresist which shows a positive-type, a negative- type, and an intermediate-type reaction to exposure light. Three regions, a gate region 2804, a high source region 2806, and a high drain region 2808 are provided to the side wall spacer troughs 2801 and 2802, and a residual negative- type pattern 2526 and a residual hard mask layer 2408 are formed. By this setup, a CMOS device can be improved in latch-up resistance.

公开(公告)号：JPH10335486A

公开(公告)日：1998-12-18

申请号：JP12100598

申请日：1998-04-30

Applicant: IBM

Inventor： JEFFREY S BROWN ,  STEPHEN J HORMES ,  LEIDY ROBERT K ,  VOLDMAN STEVEN H

IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/866

Abstract: PROBLEM TO BE SOLVED: To form a buried Zener diode having a sufficiently low breakdown voltage level, by generating a self-aligning Zener diode by executing a two-state photography mask process in a hybrid photoresist process. SOLUTION: A positive line pattern is formed on an N-well area, and a negative line pattern is formed on the other area than the N-well area. After N-well sedge implant 2302 is formed, the positive line pattern is removed and an N-well 2402 is formed. Then, a positive line pattern 2510 is formed on a p-well area and a negative line pattern 2508 is formed on the other area than the P-well area. Thereafter, an embedded Zener diode is formed by forming P-well edge implant 2602. Therefore, the number of required process masks can be reduced and the alignment problem of the photolightography can be reduced.

公开(公告)号：JPH10321807A

公开(公告)日：1998-12-04

申请号：JP12094798

申请日：1998-04-30

Applicant: IBM

Inventor： FEI D BAKER ,  JEFFREY S BROWN ,  ROBERT J GAUZAR ,  STEPHEN J HORMES ,  ROBERT K LADY ,  EDWARD J NOWACK ,  VOLDMAN STEVEN H

IPC: H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To improve the latch-up resistance of a CMOS device by forming implants on the edges of an N well and/or a P well by using a hybrid resist and, at the same time, to improve the device density of the CMOS device by promoting the scaling of the device. SOLUTION: A wafer section 2100 can be completed by an appropriate manufacturing method, for example, by forming a device gate, a contact diffusion area, etc. In the wafer section 2100, in addition, N and P contact diffusion areas are formed. In these contact diffusion areas, implants are usually formed on the surface of silicon which is not masked with a polysilicon gate. Therefore, a method and a structure for reducing the latch-up of a CMOS device by forming N and/or P edge implants on the edges of a P-well, N-well, and/or a double well are obtained.