公开(公告)号：EP1599904A4

公开(公告)日：2006-04-26

申请号：EP02786852

申请日：2002-12-03

Applicant: IBM

Inventor： MANDELMAN JACK ,  VOLDMAN STEVEN H

IPC: H01L21/336 ,  H01L23/62 ,  H01L27/02 ,  H01L27/12 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01

CPC classification number: H01L29/7841 ,  H01L27/0255 ,  H01L27/1203 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/78684 ,  H01L2029/7857

Abstract: An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (50) (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate (60). The gate (60) may be connected to the external electrode (51) being protected to make a self-activating device and may be connected to a reference voltage (92). The device may be used in digital or analog circuits.

公开(公告)号：EP1745515A4

公开(公告)日：2009-04-01

申请号：EP04822011

申请日：2004-04-22

Applicant: IBM

Inventor： FREEMAN GREGORY G ,  RIEH JAE-SUNG ,  SHERIDAN DAVID C ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D ,  VOLDMAN STEVEN H

IPC: H01L29/00 ,  H01L21/331 ,  H01L21/332 ,  H01L29/08 ,  H01L29/737 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

CPC classification number: H01L29/66363 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/66242 ,  H01L29/7378 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

公开(公告)号：JP2000357732A

公开(公告)日：2000-12-26

申请号：JP2000124263

申请日：2000-04-25

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  ROBERT J GAUTHIER JR ,  MANN RANDY W ,  VOLDMAN STEVEN H

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for improving latch up characteristic of a semiconductor element. SOLUTION: Dual depth STI 20 is used for mutually separating wells. A trench contains a first substantially horizontal face in a first depth and a second substantially horizontal face in a second depth which is deeper than the first depth. An n-well 26 and a p-well 28 are formed on the respective sides of the trench. A heavily-doped region 18 is formed below the second substantially horizontal face of the trench in a substrate. The heaving-doped region is adjacent to the first and second wells, and the separation of the trench is extended.

公开(公告)号：JPH1197449A

公开(公告)日：1999-04-09

申请号：JP12084598

申请日：1998-04-30

Applicant: IBM

Inventor： BROWN JEFFREY S ,  HOLMES STEVEN J ,  LEIDY ROBERT K ,  VOLDMAN STEVEN H

IPC: H01L27/04 ,  G03F7/004 ,  H01L21/027 ,  H01L21/329 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/861

Abstract: PROBLEM TO BE SOLVED: To suppress a heat runway and improve stability of an ESD-inhibiting device in conjunction with a device scaling, by forming an in-plant under a shallow trench separation part of an ESD device. SOLUTION: An in-plant is formed under a trench separation structure of an ESD(Electrostatic Discharge) device. The in-plant is formed using a hybrid- resist. The hybrid resist formed the in-plant without any additional treatment such as mask-step. An ESD structure of a water part 2100 provides an ESD- inhibiting device function by connecting its input to the ESD device. A P++ diffusion part 2908 and an N-well 2920 constitute the first diode, and the P++ diffusion part 2908 becomes an anode and the N-well 2920 a cathode. Similarly, an N++ diffusion part 2904 and an N-well 2922 which are combined form a cathode of the second diode, and a P-type board becomes an anode.

公开(公告)号：JP2005303291A

公开(公告)日：2005-10-27

申请号：JP2005100985

申请日：2005-03-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SANDA NAOKO PIA ,  VOLDMAN STEVEN H ,  WEGER ALAN J

IPC: G01R31/00 ,  G01R31/28 ,  G01R31/308 ,  G01R31/311 ,  G06F17/50 ,  H01L21/66

CPC classification number: G01R31/308

Abstract: PROBLEM TO BE SOLVED: To provide a method, a system, and an apparatus for operating a picosecond imaging circuit analysis (PICA)/high-current source system. SOLUTION: The picosecond imaging circuit analysis (PICA)/high current source system includes a step for applying a pulse from a high current pulse source to a device under test (DUT). A photodetector detects photon emission from the DUT. Using a signal from the photodetector, the photon emission from the DUT is mapped. A data processing means relates photon emission to a specific feature of the DUT. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于操作皮秒成像电路分析（PICA）/大电流源系统的方法，系统和装置。 皮秒成像电路分析（PICA）/高电流源系统包括将高电流脉冲源的脉冲施加到被测器件（DUT）的步骤。 光电检测器检测来自DUT的光子发射。 使用来自光电检测器的信号，映射来自DUT的光子发射。 数据处理装置将光子发射与DUT的特定特征相关联。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2000332101A

公开(公告)日：2000-11-30

申请号：JP2000131432

申请日：2000-04-28

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  BRYANT ANDRES ,  ROBERT J GAUTHIER JR ,  MANN RANDY W ,  VOLDMAN STEVEN H

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-insulator(SOI) element having both an element which is completely depleted and an element which is partially depleted on a common substrate. SOLUTION: The semiconductor structure which has a continuous buried oxide layer 24 and multiple trench separate structures 33 and 35 and its formation are disclosed. The buried oxide layer is arranged in the substrate at >=2 trench separate structures in depth. The trench separate structures are variable in depth and it is not important whether the trench separate structures are in contact with the buried oxide layer or not. The two trench separate structures enter the substrate to the same or different depths. The trench separate structures provide insulating separation between areas in the substrate and the separated areas may include a semiconductor element. The semiconductor structure makes it easy to provide a digital element and an analog element on a common wafer. The dual-depth buried oxide layer facilitates the formation of an asymmetrical semiconductor structure.

公开(公告)号：JPH10321868A

公开(公告)日：1998-12-04

申请号：JP9131998

申请日：1998-04-03

Applicant: IBM

Inventor： MATTHEW J RATTEN ,  VOLDMAN STEVEN H

IPC: H01L21/768 ,  H01L21/336 ,  H01L21/84 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a SOI semiconductor device, including a conductive stud for connecting a bulk active device and a SOI(silicon-on-insulator) device with each other. SOLUTION: Substrates 20, 23 are isolated by an embedded insulating layer 22, and there are injected substances for source and drain of the opposite polarities on layer regions 24, 25. An electrical connection 26 is partly isolated by an insulator 27 and an upper insulator 28. A region 21 is made of an injected substance of the same polarity or of opposite polarity to that of the bulk substrate 20. In the case where the dopants of the regions 23, 21, 20 have the same polarity, a SOI MOSFET body is a bulk contact or a thermal joint, and functions as a SOI MOSFET body contact. In the case where the dopants of the regions 23, 21 have the same polarity while the dopant of the region 20 has the opposite polarity, the SOI MOSFET body and the region 21 form a diode for the bulk substrate, which can be used for the polarity of the dopant used, for an example, in circuit application, voltage clamp, ESD(electrostatic discharge) protection, and other circuit functions.

公开(公告)号：AU2002351206A1

公开(公告)日：2004-06-23

申请号：AU2002351206

申请日：2002-12-03

Applicant: IBM

Inventor： VOLDMAN STEVEN H ,  MANDELMAN JACK

IPC: H01L21/336 ,  H01L23/62 ,  H01L27/02 ,  H01L27/12 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01

公开(公告)号：JP2007043172A

公开(公告)日：2007-02-15

申请号：JP2006209613

申请日：2006-08-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： VOLDMAN STEVEN H

IPC: H01L25/065 ,  H01L21/822 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L27/04

CPC classification number: H01L23/60 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2924/12044 ,  H01L2924/3011 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a structure for protecting an integrated circuit chip from other voltage fluctuations which are possible to give a static discharge (ESD) or a damage, and the method of manufacturing the structure.
SOLUTION: The invention relates to a static discharge (ESD) protection structure between chips for a high speed and high frequency device comprising one or more direct transmission paths between chips. The invention specifically relates to the structure comprising (1) a first chip comprising a first circuit, (2) a second chip comprising a second circuit, and (3) an intermediate insulating layer arranged between the first chip and the second chip. The first circuit and the second circuit form a signal transmission path for transmitting a signal via the intermediate insulating layer. A static discharge (ESD) protection path is formed in the structure between the first chip and the second chip via the intermediate insulating layer, and protects the signal transmission path from ESD damage.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于保护集成电路芯片免受可能产生静电放电（ESD）或损坏的其它电压波动的结构以及制造该结构的方法。 解决方案：本发明涉及一种用于高速和高频器件的芯片之间的静电放电（ESD）保护结构，其包括芯片之间的一个或多个直接传输路径。 本发明具体涉及包括（1）包括第一电路的第一芯片，（2）包括第二电路的第二芯片和（3）布置在第一芯片和第二芯片之间的中间绝缘层的结构。 第一电路和第二电路形成用于经由中间绝缘层发送信号的信号传输路径。 通过中间绝缘层在第一芯片和第二芯片之间的结构中形成静电放电（ESD）保护路径，并保护信号传输路径免受ESD损坏。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003068754A

公开(公告)日：2003-03-07

申请号：JP2002193698

申请日：2002-07-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： LANZEROTTI LOUIS D ,  VOLDMAN STEVEN H

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor bipolar transistor structure which is improved in anti-electrostatic discharge (ESD), and to provide a manufacturing method thereof. SOLUTION: This semiconductor structure includes a bipolar transistor comprising an intrinsic base of a low impurity concentration, a high impurity concentration external base which is adjacent to the intrinsic base and has a doping transition boundary between the high impurity concentration base and the low impurity concentration base, and whose doping transition boundary between the high impurity concentration base and the low impurity concentration base is decided by the end of a window, and a silicide region extending onto the external base, containing the silicide region totally away from the window.

Abstract translation: 要解决的问题：提供一种改进了抗静电放电（ESD）的半导体双极晶体管结构，并提供其制造方法。 解决方案：该半导体结构包括双极晶体管，其包括低杂质浓度的本征基极，与本征基极相邻的高杂质浓度外部基极，并且在高杂质浓度基底与低杂质浓度基底之间具有掺杂跃迁边界 并且其高杂质浓度基极与低杂质浓度基底之间的掺杂跃迁边界由窗口末端决定，并且硅化物区域延伸到外部基底上，其中硅化物区域完全远离窗口。