公开(公告)号：AT232313T

公开(公告)日：2003-02-15

申请号：AT99973434

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：AU1397600A

公开(公告)日：2000-07-03

申请号：AU1397600

申请日：1999-11-30

Applicant: IBM

Inventor： DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：CA2349662C

公开(公告)日：2003-02-18

申请号：CA2349662

申请日：1999-11-30

Applicant: IBM

Inventor： DEBACKER PHILIPPE LOUIS ,  GLASCO DAVID BRIAN ,  DEAN MARK EDWARD ,  ROCKHOLD RONALD LYNN ,  CARPENTER GARY DALE

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nod es coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs . Although each external interrupt domain typically includes only a single nod e, interrupt channelling or interrupt funnelling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrup ts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system.

公开(公告)号：CA2349662A1

公开(公告)日：2000-06-22

申请号：CA2349662

申请日：1999-11-30

Applicant: IBM

Inventor： ROCKHOLD RONALD LYNN ,  GLASCO DAVID BRIAN ,  DEBACKER PHILIPPE LOUIS ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nod es coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs . Although each external interrupt domain typically includes only a single nod e, interrupt channelling or interrupt funnelling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrup ts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system.

公开(公告)号：PL348253A1

公开(公告)日：2002-05-20

申请号：PL34825399

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F9/48 ,  G06F15/173 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：HU0104536A2

公开(公告)日：2002-03-28

申请号：HU0104536

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  DEBACKER PHILIPPE LOUIS ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F9/48 ,  G06F15/173 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：CZ20012154A3

公开(公告)日：2001-09-12

申请号：CZ20012154

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：IE990580A1

公开(公告)日：2000-06-28

申请号：IE990580

申请日：1999-07-09

Applicant: IBM

Inventor： DEAN MARK E ,  ROCKHOLD RONALD LYNN ,  MAGEE JAMES MICHAEL ,  FLEET JAMES VAN ,  JR GUY G SOTOMAYOR

IPC: G06F20060101 ,  G06F9/50 ,  G06F11/34 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00 ,  G06F13/14 ,  G06F15/80

Abstract: A method and system in a distributed shared-memory data processing system are disclosed having a single operating system being executed simultaneously by a plurality of processors included within a plurality of coupled processing nodes for determining a utilization of each memory location included within a shared-memory included within each of the plurality of nodes by each of the plurality of nodes. The operating system processes a designated application utilizing the plurality of nodes. During the processing, for each of the plurality of nodes, a determination is made of a quantity of times each memory location included within a shared-memory included within each of the plurality of nodes is accessed by each of the plurality of nodes.