公开(公告)号：EP1875516A4

公开(公告)日：2008-08-13

申请号：EP06739771

申请日：2006-03-27

Applicant: IBM

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L21/8244 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区和体硅区的衬底，其中SOI区和体硅区具有相同或不同的结晶取向; 隔离SOI区域与体硅区域的隔离区域; 以及位于所述SOI区域中的至少一个第一器件和位于所述体硅区域中的至少一个第二器件。 SOI区域在绝缘层顶上具有硅层。 体硅区还包括位于第二器件下方的阱区和与阱区的接触，其中接触稳定了浮体效应。 阱接触也用于控制体硅区域中的FET的阈值电压，以优化由SOI和体硅区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：JP2002185308A

公开(公告)日：2002-06-28

申请号：JP2001326092

申请日：2001-10-24

Applicant: IBM

Inventor： KARTSCHOKE PAUL D ,  ROHRER NORMAN J

IPC: H03K19/20 ,  H03K3/356 ,  H03K19/00 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To provide a circuit and method which decrease a DC power consumption amount of a clock type ratio digital logic circuit. SOLUTION: This circuit analyzes a voltage transition of a ratio digital logic circuit 160, and a switching circuit 150 controls a DC current which flows in the entire circuit based on the transition. By adjusting the DC current flowing in the digital logic circuit, a hot electronic action which puts an obstacle in the digital circuit and problematic harmful influences of electric movement are decreased. This circuit and method are exemplified by a ratio logic NOR function which utilizes a MOSFET technique.

公开(公告)号：JP2006024330A

公开(公告)日：2006-01-26

申请号：JP2004203670

申请日：2004-07-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FIFIELD JOHN A ,  KARTSCHOKE PAUL D ,  KLAASEN WILLIAM A ,  KOSONOCKY STEPHEN V ,  RANDY W MANN ,  OPPOLD JEFFERY H ,  ROHRER NORMAN J

IPC: G11C11/41 ,  G01T1/17 ,  G11C29/04 ,  H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a detection circuit and a method for detecting silicon well voltage or current indicating collision of an alpha particle or a cosmic ray to the silicon well in silicon substrate.
SOLUTION: An effective application of the detection circuit is use in redundancy repair latches used for an SRAM. In the redundancy repair latches, normally writing is once performed when power is on in order to register wrong latch data, though writing is not performed again usually. When either state of these latches is altered by SER phenomena (soft error rate: collision of the alpha particle or the cosmic ray, and the like), the recovery data for the redundant latch of the SRAM is mapped incorrectly. In this detection circuit and the method, whether the SER phenomenon occurs in these latches is monitored, when occurring, reloading the recovery data is performed to the redundancy repair latches.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供检测电路和检测硅阱电压或电流的方法，所述硅阱电压或电流指示α粒子或宇宙射线与硅衬底中的硅阱的碰撞。

解决方案：检测电路的有效应用是用于SRAM的冗余修复锁存器中。 在冗余修复锁存器中，通常只有在通电时才进行写入操作，才能注册错误的锁存器数据，但通常不会再写入。 当这些锁存器的任一状态被SER现象（软错误率：α粒子或宇宙射线的碰撞等）改变时，SRAM的冗余锁存器的恢复数据被映射不正确。 在该检测电路和方法中，监视这些锁存器中是否发生SER现象，发生时，对冗余修复锁存器进行恢复数据的重新加载。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006013114A

公开(公告)日：2006-01-12

申请号：JP2004187616

申请日：2004-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COTTRELL PETER E ,  DENNARD ROBERT H ,  EDWARD J NOWAKU ,  ROHRER NORMAN J

IPC: H01L27/14 ,  G01T1/24 ,  H01L29/74 ,  H01L29/786 ,  H01L31/09

Abstract: PROBLEM TO BE SOLVED: To provide a radiation detector formed by using a silicon-on insulator technology.
SOLUTION: The radiation detector comprises a silicon layer formed on an insulating substrate and having a PNPN structure, and a gate layer formed on the PNPN structure and having a PN gate. Latch-up occurs only in response to incident radiation in the radiation detector. In a second mode, the radiation detector has a silicon-on insulator PNPN diode structure and latch-up occurs only in response to incident radiation in the radiation detector. In a third mode, a silicon-on insulator radiation detector has a silicon layer formed on the insulating substrate, the silicon layer has the PNPN structure and a gate layer formed thereon, the gate layer has a PN gate, and latch-up occurs only in response to incident radiation in the radiation detector.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过使用硅绝缘体技术形成的辐射检测器。 解决方案：辐射检测器包括形成在绝缘衬底上并具有PNPN结构的硅层和形成在PNPN结构上并具有PN栅极的栅极层。 仅在响应于辐射探测器中的入射辐射时发生闩锁。 在第二种模式中，辐射探测器具有硅上绝缘体PNPN二极管结构，并且只在响应于辐射探测器中的入射辐射而发生闩锁。 在第三种模式中，硅绝缘体辐射探测器具有形成在绝缘衬底上的硅层，硅层具有PNPN结构和形成于其上的栅极层，栅极层具有PN栅极，并且仅闩锁发生 响应辐射检测器中的入射辐射。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2006113061A2

公开(公告)日：2006-10-26

申请号：PCT/US2006011167

申请日：2006-03-27

Applicant: IBM ,  CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L29/94

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种包括具有SOI区域和体硅区域的衬底的6T-SRAM半导体结构，其中SOI区域和体硅区域具有相同或不同的晶体取向; 将SOI区域与本体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层的顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。