公开(公告)号：EP2522027A4

公开(公告)日：2014-05-28

申请号：EP11732060

申请日：2011-01-05

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG HSUN ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78612 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66772

Abstract: In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.

公开(公告)号：EP2522032A4

公开(公告)日：2014-05-28

申请号：EP11732064

申请日：2011-01-05

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78615

Abstract: In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

公开(公告)号：EP2396812A4

公开(公告)日：2012-08-01

申请号：EP10767544

申请日：2010-04-15

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  MO RENEE T ,  NARAYANAN VIJAY ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7856 ,  H01L29/66795

公开(公告)号：EP1875516A4

公开(公告)日：2008-08-13

申请号：EP06739771

申请日：2006-03-27

Applicant: IBM

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L21/8244 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区和体硅区的衬底，其中SOI区和体硅区具有相同或不同的结晶取向; 隔离SOI区域与体硅区域的隔离区域; 以及位于所述SOI区域中的至少一个第一器件和位于所述体硅区域中的至少一个第二器件。 SOI区域在绝缘层顶上具有硅层。 体硅区还包括位于第二器件下方的阱区和与阱区的接触，其中接触稳定了浮体效应。 阱接触也用于控制体硅区域中的FET的阈值电压，以优化由SOI和体硅区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：JP2011048894A

公开(公告)日：2011-03-10

申请号：JP2010180536

申请日：2010-08-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MONTOYE ROBERT KEVIN ,  DITLOW GARY ,  JI BRIAN L ,  CHANG LELAND

IPC: G11C15/04 ,  G11C13/00

CPC classification number: G11C15/046 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004

Abstract: PROBLEM TO BE SOLVED: To provide a memory device used particularly for an associative memory, a method for operating the associative memory, and a system including the associative memory. SOLUTION: The memory device for storing one or a plurality of addresses includes a coincidence line and first and second memory cells forming a two-bit memory cell. Each memory cell includes two memory elements connected to the coincidence line, and a selection line connected there. The selection line provides a signal expression of logical combinations of at least two different inputs. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供特别用于关联存储器的存储器件，用于操作关联存储器的方法以及包括关联存储器的系统。 解决方案：用于存储一个或多个地址的存储器件包括一致线和形成两位存储器单元的第一和第二存储器单元。 每个存储单元包括连接到重合线的两个存储元件，以及连接在该存储单元上的选择线。 选择线提供至少两个不同输入的逻辑组合的信号表达。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010258471A

公开(公告)日：2010-11-11

申请号：JP2010155374

申请日：2010-07-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHANG LELAND ,  CHOU ANTHONY I ,  NARASIMHA SHREESH ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To mount a body contact on a semiconductor-on-insulator device, thereby reducing parasitic capacitance in the device. SOLUTION: A substrate includes a semiconductor layer arranged so as to be covered on an insulating layer. The semiconductor layer includes the substrate including a semiconductor body and an separation region existing around the outer periphery of the semiconductor body, and a gate structure covered on the semiconductor layer of the substrate. A method for manufacturing a semiconductor device is provided. The semiconductor device includes the gate structure existing on a first part of an upper face of the semiconductor body and a silicide body contact directly physically brought into contact with a second part of the semiconductor body separated from the first part of the semiconductor body by a non-silicide semiconductor region. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：将绝缘体上的半导体器件接触，从而减少器件中的寄生电容。 解决方案：衬底包括布置成被覆盖在绝缘层上的半导体层。 半导体层包括包括半导体本体的基板和存在于半导体主体的外周周围的分离区域，以及覆盖在基板的半导体层上的栅极结构。 提供一种制造半导体器件的方法。 该半导体器件包括存在于半导体本体的上表面的第一部分上的栅极结构和直接物理地与半导体本体的第一部分分离的半导体主体的第二部分接触的硅化物体接触， 硅化物半导体区域。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2006113061A2

公开(公告)日：2006-10-26

申请号：PCT/US2006011167

申请日：2006-03-27

Applicant: IBM ,  CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L29/94

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种包括具有SOI区域和体硅区域的衬底的6T-SRAM半导体结构，其中SOI区域和体硅区域具有相同或不同的晶体取向; 将SOI区域与本体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层的顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：WO2013052935A1

公开(公告)日：2013-04-11

申请号：PCT/US2012059152

申请日：2012-10-06

Applicant: IBM ,  CHANG JOSEPHINE B ,  CHANG LELAND ,  ENGELMANN SEBASTIAN U ,  GUILLORN MICHAEL A

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  ENGELMANN SEBASTIAN U ,  GUILLORN MICHAEL A

IPC: H01L29/66

CPC classification number: B81C1/0023 ,  B81B2207/015 ,  B81C1/00801 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/565 ,  H01L21/845 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

Abstract translation: 用于制造在基板上分离机电装置和CMOS装置的阻挡层的结构和方法。 示例性结构包括封装机电装置的保护层，其中阻挡层可以承受能够去除保护层而不是阻挡层的蚀刻工艺。 衬底可以是绝缘体上硅或多层晶片衬底。 机电装置可以是微机电系统（MEMS）或纳米机电系统（NEMS）。

公开(公告)号：WO2013151625A2

公开(公告)日：2013-10-10

申请号：PCT/US2013026779

申请日：2013-02-20

Applicant: IBM

Inventor： CHANG LELAND ,  LIN CHANG-HSUN ,  LO SHIH-HSIEN ,  SLEIGHT JEFFREY W

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/6659

Abstract: A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.

Abstract translation: 一种静态随机存取存储器制造方法包括在衬底上形成栅极堆叠，在栅极叠层附近形成隔离间隔物，隔离间隔物和栅极叠层具有栅极长度，形成与栅极堆叠相邻的源极和漏极区域，其产生有效的 栅极长度，其中源极和漏极区域由改变栅极长度和有效栅极长度之间的差异的低延伸剂量注入形成。

公开(公告)号：WO2011084975A3

公开(公告)日：2011-12-29

申请号：PCT/US2011020173

申请日：2011-01-05

Applicant: IBM ,  CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78615

Abstract: In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

Abstract translation: 在本发明的一个示例性实施例中，非对称N型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。 在另一示例性实施例中，非对称N型场效应晶体管可用作对称N型场效应晶体管。