公开(公告)号：JPH05160251A

公开(公告)日：1993-06-25

申请号：JP14874592

申请日：1992-05-15

Applicant: IBM

Inventor： KURAUSU DEIITORIKU BEIYAA ,  RUISU RUUCHIEN SHIYU ,  SUBODO KESHIYAFU KURUKAANI

IPC: H01L21/76 ,  H01L21/764

Abstract: PURPOSE: To improve a method of forming an isolation trench which is filled with air in a semiconductor substrate. CONSTITUTION: An isometrical CVD silicon dioxide 38 is deposited on an inactivated surface 19 of a semiconductor substrate. Then, a crossed trench is formed, and the crossed trench is partially filled up with a water-soluble glass and a polymer material such as polyimide, which can be continuously removed from under the isometrical CVD silicon dioxide 38. The isometric CVD silicon dioxide 38 is etched back up to the inactivated surface 19 of the semiconductor substrate, and an opening is provided to the isometric CVD silicon dioxide 38 at a trench intersection, so as to reach a trench-filled material. The filling material is removed through the opening. An anisometric CVD silicon dioxide 48 is deposited to fill up the opening, and the silicon dioxide cap 38 is left to bridge the trench filled with air.

公开(公告)号：JPH07254653A

公开(公告)日：1995-10-03

申请号：JP11110493

申请日：1993-04-14

Applicant: IBM

Inventor： TAKI NASERU BUCHI ,  RUISU RUUCHIEN SHIYU ,  MAAKU EDOUIN JIYOSUTO ,  SEIKI OGURA ,  RONARUDO NOOMAN SHIYURUTSU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786

Abstract: PURPOSE: To form a thin silicon region for a CMOS and a thick silicon region for a bipolar region into an epitaxial device layer. CONSTITUTION: A set of oxide islands 20 is formed onto a first wafer. An epitaxial layer 30 is grown from a bipolar silicon region, and the oxide islands 20 are coated. The process is used as a step, when the bottom section of a bipolar region is formed. The first wafer is inverted, and an oxide is coupled with a second wafer 60 by the new grown epitaxial layer 30 in the lower sections of the oxide islands 20. Consequently, a new top face is formed in a high-quality epitaxial layer. Excess silicon is removed from the new top face, the top face is polished by using a nitride polishing stop layer until thickness on the oxide islands 20 reaches 1000 (Å), and the thick epitaxial silicon layer of 1 (μm) is left in the bipolar region, while the epitaxial silicon layer of thickness 1000 (Å) is left in a CMOS region.