公开(公告)号：JPS60124824A

公开(公告)日：1985-07-03

申请号：JP14981484

申请日：1984-07-20

Applicant: IBM

Inventor： FUANGUUSHI YORUDAN RAI ,  RONARUDO NOOMAN SHIYURUTSU

IPC: H01L21/302 ,  H01L21/3065

公开(公告)号：JPH07254653A

公开(公告)日：1995-10-03

申请号：JP11110493

申请日：1993-04-14

Applicant: IBM

Inventor： TAKI NASERU BUCHI ,  RUISU RUUCHIEN SHIYU ,  MAAKU EDOUIN JIYOSUTO ,  SEIKI OGURA ,  RONARUDO NOOMAN SHIYURUTSU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786

Abstract: PURPOSE: To form a thin silicon region for a CMOS and a thick silicon region for a bipolar region into an epitaxial device layer. CONSTITUTION: A set of oxide islands 20 is formed onto a first wafer. An epitaxial layer 30 is grown from a bipolar silicon region, and the oxide islands 20 are coated. The process is used as a step, when the bottom section of a bipolar region is formed. The first wafer is inverted, and an oxide is coupled with a second wafer 60 by the new grown epitaxial layer 30 in the lower sections of the oxide islands 20. Consequently, a new top face is formed in a high-quality epitaxial layer. Excess silicon is removed from the new top face, the top face is polished by using a nitride polishing stop layer until thickness on the oxide islands 20 reaches 1000 (Å), and the thick epitaxial silicon layer of 1 (μm) is left in the bipolar region, while the epitaxial silicon layer of thickness 1000 (Å) is left in a CMOS region.

公开(公告)号：JPH0615564A

公开(公告)日：1994-01-25

申请号：JP11151793

申请日：1993-05-13

Applicant: IBM

Inventor： JIEEMUZU EDOWAADO KIYARII ,  RONARUDO NOOMAN SHIYURUTSU ,  ADAMU DAN CHITSUKUNOA

IPC: B23Q3/08 ,  B24B37/30 ,  H01L21/304 ,  B24B37/04

Abstract: PURPOSE: To provide a wafer polishing jig comprising a first liquid film confined by a non-porous but flexible enclosure, and for uniformly dispersing polishing force applied to the surface of a wafer supported with the confined liquid. CONSTITUTION: This jig comprises a non-porous and flexible template having a pocket 5 reciving a wafer 7 to be polished. A washer is placed between the template pocket and a carrier 3. A water film fills the lower part of the pocket, and it is confined with the aid of the washer and by an overlying porous pad 9 extending across the pocket and having a non-porous sheath 8 facing the liquid. A second liquid film saturates and covers the upper surface of the pad. The wafer 7 to be polished floats upon the second liquid film within the pocket 5.

公开(公告)号：JPH02234435A

公开(公告)日：1990-09-17

申请号：JP727590

申请日：1990-01-18

Applicant: IBM

Inventor： GARII BERA BURONNAA ,  DEBUIDO RUIISU HAARAME ,  MAAKU EDOUIN JIYOOSUTO ,  RONARUDO NOOMAN SHIYURUTSU

IPC: H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732

Abstract: PURPOSE: To obtain a self-aligned high-speed bipolar transistor by a method wherein a second insulating region is arranged in contact with an emitter region and an extrinsic region under a fist insulating region, and an intrinsic base region is provided in the second insulating region surrounded with the emitter region and the extrinsic region. CONSTITUTION: An intrinsic base is formed as a collector on a doped silicon substrate, and an emitter mesa structure provided with a nitride side wall is formed on the intrinsic base. Then, an field insulating region is formed, and an extrinsic base region is formed in the field insulating region fully surrounding an emitter stack. An extrinsic base polysilicon is buried in this well, an insulating dielectric body is grown through thermal oxidation, and arsenic is diffused into a single crystal silicon from the emitter silicon to form an emitter. By this setup, a self-aligned high-speed bipolar transistor can be obtained.