公开(公告)号：FR2343374A1

公开(公告)日：1977-09-30

申请号：FR7702066

申请日：1977-01-18

Applicant: IBM

Inventor： CHEN CHIN L ,  RUTLEDGE ROBERT A

IPC: H04L27/18 ,  H03M13/23 ,  H04L1/00 ,  H04L1/10

Abstract: This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations:

公开(公告)号：CA1068410A

公开(公告)日：1979-12-18

申请号：CA272260

申请日：1977-02-21

Applicant: IBM

Inventor： CHEN CHIN L ,  RUTLEDGE ROBERT A

IPC: H04L27/18 ,  H03M13/23 ,  H04L1/00 ,  G06F11/12

Abstract: AN ERROR CORRECTION CODE AND APPARATUS FOR THE CORRECTION OF DIFFERENTIALLY ENCODED QUADRATURE PHASE SHIFT KEYED DATA (DQPSK) This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations: where i?, i? and i? are the three information bits in the set associated with the parity bits P? and p? while the other information bits are from the seven sets of the sequence preceding the set associated with the parity bits.

公开(公告)号：AU2295777A

公开(公告)日：1978-09-07

申请号：AU2295777

申请日：1977-03-04

Applicant: IBM

Inventor： CHEN CHIN LONG ,  RUTLEDGE ROBERT A

IPC: H04L27/18 ,  H03M13/23 ,  H04L1/00 ,  H04L1/10 ,  H04L27/20 ,  H04L27/22

Abstract: This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations:

公开(公告)号：SG44417A1

公开(公告)日：1997-12-19

申请号：SG1996000254

申请日：1991-05-09

Applicant: IBM

Inventor： RUTLEDGE ROBERT A ,  PATEL ARVIND M

IPC: G11B20/10 ,  G11B20/14 ,  H03M5/14 ,  H03M7/46 ,  H03M7/14 ,  H04L25/49

Abstract: A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved. A phase check is not necessary.

公开(公告)号：DE2704627A1

公开(公告)日：1977-09-08

申请号：DE2704627

申请日：1977-02-04

Applicant: IBM

Inventor： CHEN CHIN LONG ,  RUTLEDGE ROBERT A

IPC: H04L27/18 ,  H03M13/23 ,  H04L1/00 ,  H03K13/34 ,  H04L1/10

Abstract: This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations: