公开(公告)号：US3924113A

公开(公告)日：1975-12-02

申请号：US36838473

申请日：1973-06-08

Applicant: IBM

Inventor： GILL CHARLES D ,  RYAN PHILIP M

IPC: H01J37/305 ,  G06F17/15 ,  G06F17/17 ,  G06F17/18 ,  H01J37/304 ,  H01L21/00 ,  H01L21/027 ,  G06F15/34 ,  H01J37/28

CPC classification number: H01J37/3045 ,  H01L21/00

Abstract: In semiconductor manufacture, very accurate patterns must be formed in the photoresist on the surface of the semiconductor material. Chips are formed on a semiconductor wafer utilizing a beam of charged particles to expose the photoresist material on the surface of the semiconductor. If the plurality of chips, is to have the same characteristics and pattern, it is necessary that the electrons or beam of charged particles be moved such that any point within the field to which the beam is applied is always reached by the same history. This requires that patterns produced by an electron beam be properly registered with respect to previously generated patterns. This registration is accomplished by scanning previously placed registration marks on the chip with a beam of electrons and monitoring the reflected or back-scattered electrons to determine where the beam crosses said registration marks. The method disclosed herein is a system of processing the signals encountered during beam contact with the registration marks on the chip usually at the four corners thereof, whereby the location of the marks is accurately determined. This is accomplished by first improving the signal to noise ratio of the detected signal followed by a rapid crosscorrelation between the averaged signal and another signal having certain specific and especially desirable characteristics. The final step utilizes a least squares curve fitting procedure tuned up to extract the essential parameter, that is the center of the cross-correlation, with a minimum of on-line computation.

Abstract translation: 在半导体制造中，必须在半导体材料的表面上的光致抗蚀剂中形成非常精确的图案。 利用带电粒子束在半导体晶片上形成芯片以暴露半导体表面上的光致抗蚀剂材料。 如果多个芯片具有相同的特性和图案，则必须移动带电粒子的电子束或束，使得施加光束的场内的任何点总是达到相同的历史。 这要求由电子束产生的图案相对于先前产生的图案适当地记录。 该注册通过用电子束扫描先前放置的芯片上的注册标记并监测反射或反向散射电子来确定光束穿过所述对准标记的位置来完成。 本文公开的方法是在通常在其四个角处处理在与芯片上的对准标记的光束接触期间遇到的信号的系统，由此准确地确定标记的位置。 这是通过首先改善检测信号的信噪比，然后在平均信号与具有特定和特别期望特性的另一个信号之间的快速互相关来实现的。 最后一步利用最小二乘曲线拟合程序进行调整，以最小的在线计算提取基本参数，即互相关的中心。

公开(公告)号：US3866013A

公开(公告)日：1975-02-11

申请号：US39873473

申请日：1973-09-19

Applicant: IBM

Inventor： RYAN PHILIP M

IPC: H01J37/147 ,  H01J37/302 ,  H01L21/027 ,  H05K3/00 ,  B23K15/00

CPC classification number: H01J37/3023

Abstract: A square-shaped electron beam is stepped from one predetermined position to another in a line-by-line scan to form a desired pattern on each chip of a semiconductor wafer to which the beam is applied. At each of the predetermined positions, the beam is on, off, or on for a portion of the time period at which the beam is disposed at the predetermined position. The beam also can be offset both along its direction of movement and perpendicular thereto at each of the predetermined positions. Control of this movement of the beam is obtained through utilizing a memory with no change being made in the memory if the predetermined position at the next line does not have any change from the predetermined position at the line along which the beam is moving.

Abstract translation: 在逐行扫描中，从一个预定位置到另一个位置的方形电子束形成在施加光束的半导体晶片的每个芯片上的期望图案。 在每个预定位置处，光束在光束被布置在预定位置的时间段的一部分时间被接通，断开或接通。 在每个预定位置处，光束也可以沿其运动方向和垂直于其两者偏移。 如果在下一行的预定位置与波束移动的线上的预定位置没有任何变化，则通过利用不改变存储器的存储器来获得波束的这种运动的控制。

公开(公告)号：DE3379123D1

公开(公告)日：1989-03-09

申请号：DE3379123

申请日：1983-05-27

Applicant: IBM

Inventor： RYAN PHILIP M

IPC: G06F12/16 ,  G11C29/00 ,  G06F11/00

Abstract: A method is disclosed for insuring that two semiconductor chips which have a 1-bit defect at the same on-chip address are not paired at any memory address by a fault alignment exclusion mechanism (FAEM) which functions to position chips having such defects at different memory addresses. The FAEM employs an error map to determine which chips must be realigned in their respective columns and an address permute vector functions to effectively change the physical address of the chip in the column to a logical address. The two permute vectors for the two columns contributing to any new uncorrectable error are "exclusive-ORed" and the result stored in a second map along with an identification of the chip columns. This map is termed the forbidden result table. Any time in the future that a new permute vector is proposed for assignment to any column of chips, the changed permute vector is exclusive-ORed with the permute vectors currently assigned to all other columns of the memory to see if any such combination produces a result forbidden by the forbidden result table. If no such forbidden result is found, the proposed permute vector can be assigned with the assurance that no pair of chips previously found to produce aligned faults will align now in any row of the memory. If any forbidden result is found, the proposed permute vector is discarded and a new one proposed.

公开(公告)号：CA1166766A

公开(公告)日：1984-05-01

申请号：CA291957

申请日：1977-11-29

Applicant: IBM

Inventor： PFEIFFER HANS C ,  RYAN PHILIP M ,  WEBER EDWARD V

IPC: H01J37/147 ,  H01J37/09 ,  H01J37/30 ,  H01L21/027 ,  G21K1/08 ,  B23K15/00 ,  H01L21/42

Abstract: In electron beam apparatus having a source of electrons and a target area toward which the electrons are directed, electron beam forming means are provided along the path from the source to the target. These forming means include a first beam shaping member having a first spot shaping aperture therein, a second beam shaping member having a second spot shaping aperture therein, and means focusing the image of the first aperture in the plane of the second aperture to thereby form a composite spot shape defined by the image of the first aperture and the second aperture. Further means are provided for focusing the image of the composite spot in the target area. Preferably, the apertures are square shaped. Thus, by varying the position of the superimposed image of the first aperture with respect to the second aperture, a wide variety of rectangular shaped composite spots with different dimensions is obtainable. This permits the exposure of rectilinear patterns, e.g., in photoresists of integrated circuit fabrication, by the electron beam with a minimum of exposure steps and substantially no exposure overlap. The result is greatly increased speed in the total exposure of such rectilinear areas to the electron beam as well as a minimum of the "blooming effects" produced by exposure overlap.

公开(公告)号：FR2382091A1

公开(公告)日：1978-09-22

申请号：FR7800742

申请日：1978-01-05

Applicant: IBM

Inventor： PFEIFFER HANS C ,  RYAN PHILIP M ,  WEBER EDWARD V

IPC: H01J37/147 ,  H01J37/09 ,  H01J37/30 ,  H01L21/027 ,  H01J37/21 ,  H01L21/306

公开(公告)号：DE2443625A1

公开(公告)日：1975-03-20

申请号：DE2443625

申请日：1974-09-12

Applicant: IBM

Inventor： RYAN PHILIP M

IPC: H01J37/147 ,  H01J37/302 ,  H01L21/027 ,  H05K3/00 ,  H01J37/00 ,  H01L21/68

公开(公告)号：DE3379753D1

公开(公告)日：1989-06-01

申请号：DE3379753

申请日：1983-05-27

Applicant: IBM

Inventor： BOND GEORGE L ,  CARTMAN FRANK P ,  RYAN PHILIP M

IPC: G06F12/16 ,  G11C29/00 ,  G06F11/00

Abstract: A fault alignment exclusion method and apparatus is disclosed which operates to prevent the alignment of two or more defective bit storage locations at an address in a memory array. The disclosed memory comprises a plurality (n x m) of separate memory chips (71) arranged in a matrix of n rows and m columns. Each of the chips contains a large plurality (64K) of individually addressable bit locations. A plurality of data words, each containing m (72) bit positions are transferred from the memory array to a n' (16) word m (72) bit position buffer during a memory read operation. Steering logic (35) responsive to control signals (R5-R8) is disposed between the memory and the buffer which permits the n (32) chips in each column of the array to be effectively rearranged selectively within the respective columns so that the relationship of any given chip to a position of the 16 storage positions in a corresponding buffer column (20) may be selectively changed by the control signals applied to the steering logic. The control signals are developed based on defect data stored in an error map such that each memory address contains no more than one defective location. An additional control signal (R2) may be used to control an address permutation logic (40) for helping to achieve the same purpose.

公开(公告)号：DE3380909D1

公开(公告)日：1990-01-04

申请号：DE3380909

申请日：1983-05-27

Applicant: IBM

Inventor： RYAN PHILIP M

IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00 ,  G06F11/00

Abstract: An online system (6) is disclosed for mapping errors into an error map (64) as read data is transferred between a relatively large fault tolerant semiconductor memory system (5) and a CPU without interfering with the normal use of the memory. The error mapping system permits a fault alignment exclusion mechanism to develop permute vectors which realign pair faults that were located at the same memory address. Having an up-to-date fault map which reflects the current error status of the memory when it is online and which reflects errors based on user data patterns greatly enhances the memory system and facilitates fault alignment exclusion efficiency.

公开(公告)号：CA1013074A

公开(公告)日：1977-06-28

申请号：CA207581

申请日：1974-08-22

Applicant: IBM

Inventor： RYAN PHILIP M

IPC: H01J37/147 ,  H01J37/302 ,  H01L21/027 ,  H05K3/00

公开(公告)号：CA1009766A

公开(公告)日：1977-05-03

申请号：CA198075

申请日：1974-04-19

Applicant: IBM

Inventor： GILL CHARLES D ,  RYAN PHILIP M

IPC: H01J37/305 ,  G06F17/15 ,  G06F17/17 ,  G06F17/18 ,  H01J37/304 ,  H01L21/00 ,  H01L21/027

Abstract: In semiconductor manufacture, very accurate patterns must be formed in the photoresist on the surface of the semiconductor material. Chips are formed on a semiconductor wafer utilizing a beam of charged particles to expose the photoresist material on the surface of the semiconductor. If the plurality of chips, is to have the same characteristics and pattern, it is necessary that the electrons or beam of charged particles be moved such that any point within the field to which the beam is applied is always reached by the same history. This requires that patterns produced by an electron beam be properly registered with respect to previously generated patterns. This registration is accomplished by scanning previously placed registration marks on the chip with a beam of electrons and monitoring the reflected or back-scattered electrons to determine where the beam crosses said registration marks. The method disclosed herein is a system of processing the signals encountered during beam contact with the registration marks on the chip usually at the four corners thereof, whereby the location of the marks is accurately determined. This is accomplished by first improving the signal to noise ratio of the detected signal followed by a rapid cross-correlation between the averaged signal and another signal having certain specific and especially desirable characteristics. The final step utilizes a least squares curve fitting procedure tuned up to extract the essential parameter, that is the center of the cross-correlation, with a minimum of on-line computation.