公开(公告)号：JP2004304190A

公开(公告)日：2004-10-28

申请号：JP2004090598

申请日：2004-03-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHATER MARWAN H ,  RIEH JAE-SUNG ,  STRICKER ANDREAS D ,  GREGORY G FREEMAN ,  SCHONENBERG KATHRYN T

IPC: H01L29/70 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a bipolar transistor structure, capable of reducing the parasitic capacitance.
SOLUTION: A method for forming a vertical bipolar transistor, comprising the steps of forming a bipolar transistor on silicon semiconductor substrate 11 which has an upper surface; forming STI regions 14 which are made of dielectric materials and have an inside edge portion and an upper surface, respectively; forming a doped collector region C between a pair of STI regions; also forming a counter doped intrinsic base region IB between the pair of STI regions, wherein there is each margin between the intrinsic base region and the pair of STI regions, and the intrinsic base region has edges; forming a doped-emitter region on the intrinsic base region apart from the edges; and forming shallow separated extension regions IE made of dielectric materials in the above margins, and placing them in parallel with the edges of the intrinsic base region; and forming an outer base region which covers the shallow separated extension regions partially, and further extends to the intrinsic base region, thereby physically and electrically contacting with the intrinsic base region.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004221582A

公开(公告)日：2004-08-05

申请号：JP2004003465

申请日：2004-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SCHONENBERG KATHRYN T ,  GREGORY G FREEMAN ,  STRICKER ANDREAS D ,  RIEH JAE-SUNG

IPC: H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligning oxide mask formed by utilizing the difference in oxidation speed between different materials.
SOLUTION: The self-aligning oxide mask is formed on a CVD growth base NPN base layer including a single crystal Si52 (Si/SiGe) in an active area and a poly-crystal Si51 (Si/SiGe). The self-aligning mask is fabricated by utilizing the fact that the poly-crystal Si (Si/SiGe) oxidizes faster than the single crystal Si (Si/SiGe). By using the thermal oxidation method, a thick oxide layer is formed on the poly-crystal Si (Si/SiGe) and a thin oxide layer is formed on the single crystal Si (Si/SiGe), thereby the oxide films are formed on both the poly-crystal Si (Si/SiGe) and the single crystal Si (Si/SiGe), and by the control of etching of the oxide, the thin oxide layer on the single crystal Si (Si/SiGe) is removed while the self-alignment oxide mask layer is left on the poly-crystal Si (Si/SiGe).
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2008135775A

公开(公告)日：2008-06-12

申请号：JP2008006982

申请日：2008-01-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COOLBAUGH DOUGLAS D ,  SCHONENBERG KATHRYN T

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/7378 ,  H01L21/26506 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/66242 ,  H01L29/66318

Abstract: PROBLEM TO BE SOLVED: To provide a method capable of not only manufacturing an SiGe hetero junction bipolar transistor but also improving the yield of an SiGe bipolar. SOLUTION: The present method includes ion implantation of carbon C into one of the following element regions i.e. a collector region, subcollector region, external base region, and collector-base junction region. In a preferred embodiment, implanted C is involved in each of the foregoing regions. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种不仅可以制造SiGe异质结双极晶体管，而且可以提高SiGe双极的产率的方法。 解决方案：本方法包括将碳C离子注入以下元件区域之一，即集电极区域，子集电极区域，外部基极区域和集电极 - 基极结区域。 在优选实施例中，植入的C涉及上述各个区域。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004319983A

公开(公告)日：2004-11-11

申请号：JP2004085745

申请日：2004-03-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SUBBANNA SESHADRI ,  JAGANNATHAN BASANTH ,  GREGORY G FREEMAN ,  AHLGREN DAVID C ,  ANGELL DAVID ,  SCHONENBERG KATHRYN T ,  STEIN KENNETH J ,  JAMIN FEN F

IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78

CPC classification number: H01L21/8249 ,  H01L27/0623

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiCMOS integrated circuit having a raised external base.
SOLUTION: This method comprises a step for forming a polycrystal silicon layer on the surface of a gate dielectric substance 18 provided on a substrate having a device section 14 in which a bipolar transistor is formed and a device section 16 in which a CMOS transistor is formed. Then, the polycrystal silicon layer is patterned, and a sacrifice polycrystal silicon layer is formed above the device section in which the bipolar transistor is formed and the section around it. Meanwhile, a gate conductor is provided in the device section in which the CMOS transistor is formed at the same time. Then, a spacer 30 is provided around each of the gate conductor. Then a part of the sacrifice polycrystal silicon layer on the bipolar device section is selectively removed to provide an opening in the device section in which the bipolar transistor is formed. Then the bipolar transistor having a raised external base 58 is formed at the opening.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成具有凸起的外部基底的BiCMOS集成电路的方法。 解决方案：该方法包括在设置在其上形成有双极晶体管的器件部分14的衬底上的栅极电介质18的表面上形成多晶硅层的步骤，以及器件部分16，其中CMOS 形成晶体管。 然后，对多晶硅层进行构图，在形成双极型晶体管的器件部分上方形成牺牲多晶硅层，并在其周围形成截面。 同时，在同时形成CMOS晶体管的器件部分中提供栅极导体。 然后，围绕每个栅极导体设置间隔件30。 然后，选择性地去除双极器件部分上牺牲多晶硅层的一部分，以在其中形成双极晶体管的器件部分中提供开口。 然后在开口处形成具有升高的外部基座58的双极晶体管。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2008134686A3

公开(公告)日：2009-12-30

申请号：PCT/US2008061938

申请日：2008-04-30

Applicant: IBM ,  KRISHNASAMY RAJENDRAN ,  GLUSCHENKOV OLEG ,  SCHONENBERG KATHRYN T

Inventor： KRISHNASAMY RAJENDRAN ,  GLUSCHENKOV OLEG ,  SCHONENBERG KATHRYN T

IPC: H01L21/331

CPC classification number: H01L29/66242 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: Disclosed is an improved semiconductor structure 150 (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor 100) having a narrow essentially interstitial-free SIC pedestal 120 with minimal overlap of the extrinsic base 104. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base 103 and collector space-charge regions than can be achieved with conventional technology.

Abstract translation: 公开了一种改进的半导体结构150（例如，硅锗（SiGe）异质结双极晶体管100），其具有窄的基本上无间隙的SIC基座120，其外部基极104具有最小的重叠。此外，公开了一种形成 使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本上无间隙的收集器的晶体管。 因此，所得到的SiGe HBT晶体管可以制造成具有比用常规技术可以实现的更窄的基极103和集电极空间电荷区域。

公开(公告)号：WO2008106574A3

公开(公告)日：2009-01-29

申请号：PCT/US2008055214

申请日：2008-02-28

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  SCHONENBERG KATHRYN T

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  SCHONENBERG KATHRYN T

IPC: H01L29/49

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.

Abstract translation: 一种结构及其形成方法。 该结构包括（a）衬底，（b）在衬底的顶部上的半导体鳍片区域，（c）半导体鳍片区域的侧壁上的栅极电介质区域，以及（d）顶部和上部的栅电极区域 半导体鳍片区域的侧壁。 栅极电介质区域（i）夹在其间并且（ii）使栅电极区域和半导体鳍片区域电绝缘。 该结构还包括在栅电极区域的第一侧壁上的第一间隔区域。 半导体鳍片区域的第一侧壁暴露于周围环境。 第一间隔区域的顶表面与栅电极区域的顶表面共面。

公开(公告)号：DE60233319D1

公开(公告)日：2009-09-24

申请号：DE60233319

申请日：2002-06-04

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  SCHONENBERG KATHRYN T

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/10 ,  H01L29/737

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region (16), the sub-collector region (14), the extrinsic base regions (29), and the collector-base junction region (27). In a preferred embodiment each of the aforesaid regions include C implants.

公开(公告)号：GB2362508B

公开(公告)日：2004-02-11

申请号：GB0027232

申请日：2000-11-07

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES S ,  GEISS PETER J ,  GRAY PETER B ,  HARAME DAVID L ,  SCHONENBERG KATHRYN T ,  ST ONGE STEPHEN A ,  SUBBANNA SESHADRI

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

公开(公告)号：GB2362508A

公开(公告)日：2001-11-21

申请号：GB0027232

申请日：2000-11-07

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES S ,  GEISS PETER J ,  GRAY PETER B ,  HARAME DAVID L ,  SCHONENBERG KATHRYN T ,  ST ONGE STEPHEN A ,  SUBBANNA SESHADRI

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method of forming a semiconductor integrated circuit such as a BiCMOS integrated circuit comprises the steps of: (a) forming a first portion of a bipolar device in a first region of a substrate; (b) forming a first protective layer over the first region to protect the first portion of the bipolar devices; (c) forming field effect transistor devices in second regions of the substrate; (d) forming a second protective layer over the second regions of the substrate to protect the field effect transistor devices; (e) removing the first protective layer; (f) forming a second portion of the bipolar devices in the first region of the substrate; and (g) removing the second protective layer.