公开(公告)号：EP1658639A4

公开(公告)日：2009-09-30

申请号：EP04777467

申请日：2004-07-01

Applicant: IBM

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L29/732 ,  H01L21/331 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

公开(公告)号：JP2011040748A

公开(公告)日：2011-02-24

申请号：JP2010178911

申请日：2010-08-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANTHONY K STAMPER ,  DUNN JAMES S ,  JOSEPH ALVIN JOSE

IPC: H01L21/3205 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L23/52 ,  H01L27/06 ,  H01L29/737

CPC classification number: H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a heterojunction bipolar transistor, and to provide a method of manufacturing the heterojunction bipolar transistor.
SOLUTION: Semiconductor structures and methods of manufacturing semiconductors relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供异质结双极晶体管，并提供制造异质结双极晶体管的方法。 解决方案：制造半导体的半导体结构和方法涉及异质结双极晶体管。 该方法包括在相同布线层上形成由金属线连接的两个器件。 两个器件中的第一个的金属线通过在铜布线结构上选择性地形成金属覆盖层而形成。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2002313798A

公开(公告)日：2002-10-25

申请号：JP2002052091

申请日：2002-02-27

Applicant: IBM

Inventor： DUNN JAMES S ,  HARAME DAVID L ,  JOHNSON JEFFREY B ,  ROBB A JOHNSON ,  LANZEROTTI LOUIS D ,  ST ONGE STEPHEN A

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide an epitaxial base bipolar transistor which has low base resistance and whose capacitance does not increase. SOLUTION: This epitaxial base bipolar transistor is provided with an epitaxial silicon layer on a single crystal semiconductor substrate 54, a raised emitter 64 on the surface of the semiconductor substrate, a raised extrinsic base 58e on the surface of the semiconductor substrate, an insulator 66 as a spacer between the raised emitter and raised extrinsic base, and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the semiconductor substrate. The emitter diffusion has an emitter diffusion junction depth, and the raised emitter extends to the surface of the semiconductor substrate and the raised extrinsic base extends to the surface of the semiconductor substrate. A difference of height between the surfaces of the emitter and base is less than 20% of the emitter diffusion junction depth.

公开(公告)号：WO2013066455A3

公开(公告)日：2014-05-08

申请号：PCT/US2012049414

申请日：2012-08-03

Applicant: IBM ,  COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETHANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETHANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.

Abstract translation: 用于粘合基板表面，粘合基板组件以及用于键合衬底组件的设计结构的方法。 使用器件衬底（10）的第一表面（15）形成产品芯片（25）的器件结构（18,19,20,21）。 在产品芯片上形成用于器件结构的互连结构的布线层（26）。 布线层被平坦化。 临时处理晶片（52）可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面（54）被结合到最终的手柄基板（56）。 然后将临时手柄晶片从组件中取出。

公开(公告)号：WO2005024900A3

公开(公告)日：2005-06-09

申请号：PCT/US2004021345

申请日：2004-07-01

Applicant: IBM ,  KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L23/62

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter (106) is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer (102) of polysilicon or silicon on an intrinsic base (108). A dielectric landing pad (128) is then formed by lithography on the first extrinsic base layer (102). Next, a second extrinsic base layer (104) of polysilicon or silicon is formed on top of the dielectric landing pad (128) to finalize the raised extrinsic base total thickness. An emitter (106) opening is formed using lithography and RIE, where the second extrinsic base layer (104) is etched stopping on the dielectric landing pad (128). The degree of self-alignment between the emitter (106) and the raised extrinsic base is achieved by selecting the first extrinsic base layer (102) thickness, the dielectric landing pad (128) width, and the spacer width.

Abstract translation: 公开了一种具有凸起的非本征基极和在本征基极和发射极（106）之间的可选自对准的双极晶体管。 制造方法可以包括在内在基极（108）上形成多晶硅或硅的第一非本征基极层（102）的预定厚度。 然后通过光刻在第一非本征基极层（102）上形成电介质着色焊盘（128）。 接下来，在电介质着色焊盘（128）的顶部上形成多晶硅或硅的第二非本征基极层（104），以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器（106）开口，其中第二外部基极层（104）被蚀刻停止在电介质着色焊盘（128）上。 通过选择第一非本征基极层（102）的厚度，电介质着陆焊盘（128）的宽度和间隔物宽度来实现发射极（106）和凸起的外在基极之间的自对准程度。

公开(公告)号：DE112012004106T5

公开(公告)日：2014-07-10

申请号：DE112012004106

申请日：2012-08-03

Applicant: IBM

Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETH-ANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

IPC: H01L21/60 ,  H01L21/58 ,  H01L23/48

Abstract: Verfahren zum Bonden von Substratoberflächen, gebondete Substratanordnungen sowie Entwurfsstrukturen für eine gebondete Substratanordnung. Es werden Einheiten-Strukturen (18, 19, 20, 21) eines Produkt-Chips (25) unter Verwendung einer ersten Oberfläche (15) eines Einheiten-Substrats (10) gebildet. Auf dem Produkt-Chip wird eine Verdrahtungsschicht (26) einer Zwischenverbindungsstruktur für die Einheiten-Strukturen gebildet. Die Verdrahtungsschicht wird planarisiert. Ein provisorischer Handhabungswafer (52) wird entfernbar an die planarisierte Verdrahtungsschicht gebondet. In Reaktion auf das entfernbare Bonden des provisorischen Handhabungswafers an die planarisierte erste Verdrahtungsschicht wird eine zweite Oberfläche (54) des Einheiten-Substrats, die entgegengesetzt zu der ersten Oberfläche ist, an ein endgültiges Handhabungssubstrat (56) gebondet. Anschließend wird der provisorische Handhabungswafer von der Anordnung entfernt.

公开(公告)号：GB2509683B

公开(公告)日：2015-07-29

申请号：GB201408711

申请日：2012-08-03

Applicant: IBM

Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETH-ANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

公开(公告)号：GB2362508B

公开(公告)日：2004-02-11

申请号：GB0027232

申请日：2000-11-07

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES S ,  GEISS PETER J ,  GRAY PETER B ,  HARAME DAVID L ,  SCHONENBERG KATHRYN T ,  ST ONGE STEPHEN A ,  SUBBANNA SESHADRI

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

公开(公告)号：GB2509683A

公开(公告)日：2014-07-09

申请号：GB201408711

申请日：2012-08-03

Applicant: IBM

Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETH-ANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.

公开(公告)号：GB2362508A

公开(公告)日：2001-11-21

申请号：GB0027232

申请日：2000-11-07

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES S ,  GEISS PETER J ,  GRAY PETER B ,  HARAME DAVID L ,  SCHONENBERG KATHRYN T ,  ST ONGE STEPHEN A ,  SUBBANNA SESHADRI

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method of forming a semiconductor integrated circuit such as a BiCMOS integrated circuit comprises the steps of: (a) forming a first portion of a bipolar device in a first region of a substrate; (b) forming a first protective layer over the first region to protect the first portion of the bipolar devices; (c) forming field effect transistor devices in second regions of the substrate; (d) forming a second protective layer over the second regions of the substrate to protect the field effect transistor devices; (e) removing the first protective layer; (f) forming a second portion of the bipolar devices in the first region of the substrate; and (g) removing the second protective layer.