公开(公告)号：EP1658639A4

公开(公告)日：2009-09-30

申请号：EP04777467

申请日：2004-07-01

Applicant: IBM

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L29/732 ,  H01L21/331 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

公开(公告)号：JP2002313798A

公开(公告)日：2002-10-25

申请号：JP2002052091

申请日：2002-02-27

Applicant: IBM

Inventor： DUNN JAMES S ,  HARAME DAVID L ,  JOHNSON JEFFREY B ,  ROBB A JOHNSON ,  LANZEROTTI LOUIS D ,  ST ONGE STEPHEN A

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide an epitaxial base bipolar transistor which has low base resistance and whose capacitance does not increase. SOLUTION: This epitaxial base bipolar transistor is provided with an epitaxial silicon layer on a single crystal semiconductor substrate 54, a raised emitter 64 on the surface of the semiconductor substrate, a raised extrinsic base 58e on the surface of the semiconductor substrate, an insulator 66 as a spacer between the raised emitter and raised extrinsic base, and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the semiconductor substrate. The emitter diffusion has an emitter diffusion junction depth, and the raised emitter extends to the surface of the semiconductor substrate and the raised extrinsic base extends to the surface of the semiconductor substrate. A difference of height between the surfaces of the emitter and base is less than 20% of the emitter diffusion junction depth.

公开(公告)号：WO2013006277A2

公开(公告)日：2013-01-10

申请号：PCT/US2012043443

申请日：2012-06-21

Applicant: IBM ,  CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  KHATER MARWAN H ,  LIU QIZHI

Inventor： CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  KHATER MARWAN H ,  LIU QIZHI

CPC classification number: H01L29/73 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/66272 ,  H01L29/7322

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.

Abstract translation: 用于制造双极结晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。 双极结晶体管（80）包括在本征基极（84）上的介电层（32）和通过介电层至少部分地与本征基极分离的外部基极（82）。 发射极开口（52）延伸穿过外部基极和电介质层。 电介质层相对于发射极开口横向凹入以限定内部基极和外部基极之间的空腔（60a，60b）。 空腔填充有将外部基极和固有基底物理连接在一起的半导体层（64）。

公开(公告)号：WO2005024900A3

公开(公告)日：2005-06-09

申请号：PCT/US2004021345

申请日：2004-07-01

Applicant: IBM ,  KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L23/62

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter (106) is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer (102) of polysilicon or silicon on an intrinsic base (108). A dielectric landing pad (128) is then formed by lithography on the first extrinsic base layer (102). Next, a second extrinsic base layer (104) of polysilicon or silicon is formed on top of the dielectric landing pad (128) to finalize the raised extrinsic base total thickness. An emitter (106) opening is formed using lithography and RIE, where the second extrinsic base layer (104) is etched stopping on the dielectric landing pad (128). The degree of self-alignment between the emitter (106) and the raised extrinsic base is achieved by selecting the first extrinsic base layer (102) thickness, the dielectric landing pad (128) width, and the spacer width.

Abstract translation: 公开了一种具有凸起的非本征基极和在本征基极和发射极（106）之间的可选自对准的双极晶体管。 制造方法可以包括在内在基极（108）上形成多晶硅或硅的第一非本征基极层（102）的预定厚度。 然后通过光刻在第一非本征基极层（102）上形成电介质着色焊盘（128）。 接下来，在电介质着色焊盘（128）的顶部上形成多晶硅或硅的第二非本征基极层（104），以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器（106）开口，其中第二外部基极层（104）被蚀刻停止在电介质着色焊盘（128）上。 通过选择第一非本征基极层（102）的厚度，电介质着陆焊盘（128）的宽度和间隔物宽度来实现发射极（106）和凸起的外在基极之间的自对准程度。

公开(公告)号：DE112011101373T5

公开(公告)日：2013-03-14

申请号：DE112011101373

申请日：2011-05-17

Applicant: IBM

Inventor： JOSEPH ALVIN J ,  STRICKER ANDREAS D ,  HARAME DAVID L ,  CAMILIO-CASTILIO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HERRIN RUSSELL T

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: Ausführungsformen einer verbesserten Transistorstruktur (100) (z. B. einer Bipolartransistor(BT)-Struktur oder Heteroübergang-Bipolartransistor(HBT)-Struktur) und ein Verfahren zur Bildung der Transistorstruktur (100) werden offenbart. Die Ausführungsformen der Struktur können eine dielektrische Schicht (130), die zwischen einer intrinsischen Basisschicht (120) und einer erhabenen extrinsischen Basisschicht (140) angeordnet ist, um die Kollektor-Basis-Kapazität Ccb zu reduzieren, einen seitenwanddefinierten leitenden Streifen (150) für eine Verbindungszone von der intrinsischen Basisschicht (120) zur extrinsischen Basisschicht (140), um den Basis-Widerstand Rb zu reduzieren, und eine dielektrische Abstandsschicht (160) zwischen der extrinsischen Basisschicht (140) und einer Emitterschicht (180) aufweisen, um die Basis-Emitter-Kapazität Cbe zu reduzieren. Die Ausführungsformen des Verfahrens erlauben die Selbstjustierung des Emitters zu Basiszonen und erlauben zudem die selektive Anpassung der Geometrien verschiedener Merkmale (z. B. der Dicke der dielektrischen Schicht (130), der Breite des leitenden Streifens (150), der Breite der dielektrischen Abstandsschicht (160) und der Breite der Emitterschicht (180)), um die Transistorleistungsfähigkeit zu optimieren.

公开(公告)号：GB2494358A

公开(公告)日：2013-03-06

申请号：GB201300063

申请日：2011-05-17

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HARAME DAVID L ,  HERRIN RUSSELL T ,  JOSEPH ALVIN ,  STRICKER ANDREAS D

IPC: H01L29/06 ,  H01L21/331 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed are embodiments of an improved transistor structure (100) (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure (100). The structure embodiments can incorporate a dielectric layer (130) sandwiched between an intrinsic base layer (120) and a raised extrinsic base layer (140) to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap (150) for an intrinsic base layer (120) to extrinsic base layer (140) link-up region to reduce base resistance Rb and a dielectric spacer (160) between the extrinsic base layer (140) and an emitter layer (180) to reduce base- emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer (130), the width of the conductive strap (150), the width of the dielectric spacer (160) and the width of the emitter layer (180)) to be selectively adjusted in order to optimize transistor performance.

公开(公告)号：DE69022864D1

公开(公告)日：1995-11-16

申请号：DE69022864

申请日：1990-01-15

Applicant: IBM

Inventor： HARAME DAVID L ,  PATTON GARY L ,  STORK JOHANNES M C

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732 ,  H01L27/08

Abstract: A transistor structure including a complementary pair of vertical bipolar transistors on a common semiconductor substrate. A first epitaxial layer (12) of semiconductor material of a first conductivity type is formed on the surface of a semiconductor substrate (10) of a second conductivity type, and a sub-emitter region for one of said complementary transistors being formed in said first layer (12). A sub-collector region (14) of a second conductivity type for the other of said complementary transistors is formed in the first layer (12). A second epitaxial layer (16) of semiconductor material of said second conductivity type is formed on the surface of said first layer (12). A third epitaxial layer (18) of semiconductor material of said first conductivity type is formed on the surface of said second layer (16). Deep recessed isolation regions (30, 32, 34) extend from the surface of said third layer (18) into said substrate (10), said deep isolation regions surround each of said transistors. Intrinsic base and collector regions (54, 56) of said one transistor are formed in said second and third layers (16, 18) respectively and intrinsic collector and base regions (58, 60) of said other transistor are formed in said second and third layers (16, 18) respectively. Shallow recessed isolation regions (44, 46, 48, 50, 52) are formed in said second and third layers (16, 18) surrounding said intrinsic base and collector regions (54, 58). A pair of extrinsic base regions (76, 78) of said first conductivity type for said other transistor and an extrinsic collector region (72) of said first conductivity type for said one transistor are formed on the surface of said third layer (18). An emitter reach-through region (74) of said first conductivity type is formed in said second and third layers (16, 18). An extrinsic base region (92) of said second conductivity type for said one transistor overlies said collector region (56) of said first conductivity type. A sub-collector reach-through region (94) of said second conductivity type is formed in said second and third layers (16, 18), and an emitter region (96) of said second conductivity type for said other transistor is formed overlying said base region (60) of said first conductivity type.

公开(公告)号：GB2506816A

公开(公告)日：2014-04-09

申请号：GB201401778

申请日：2012-06-21

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN ,  KHATER MARWAN ,  LIU QIZHI

IPC: H01L21/8249 ,  H01L29/732

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.

公开(公告)号：DE112012002434T5

公开(公告)日：2014-03-06

申请号：DE112012002434

申请日：2012-06-21

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  GRAY PETER B ,  KHATER MARWAN H

IPC: H01L29/73

Abstract: Verfahren zum Herstellen von Bipolartransistoren, Bipolartransistoren, die mittels der Verfahren hergestellt werden, sowie Entwurfsstrukturen für einen Bipolartransistor. Der Bipolartransistor (80) beinhaltet eine dielektrische Schicht (32) auf einer intrinsischen Basis (84) und eine extrinsische Basis (82), die durch die dielektrische Schicht wenigstens teilweise von der intrinsischen Basis getrennt ist. Eine Emitter-Öffnung (52) erstreckt sich durch die extrinsische Basis und die dielektrische Schicht hindurch. Die dielektrische Schicht ist lateral relativ zu der Emitter-Öffnung vertieft, um einen Hohlraum (60a, 60b) zwischen der intrinsischen Basis und der extrinsischen Basis zu definieren. Der Hohlraum ist mit einer Halbleiterschicht (64) gefüllt, welche die extrinsische Basis und die intrinsische Basis physisch miteinander verbindet.

公开(公告)号：GB2362508B

公开(公告)日：2004-02-11

申请号：GB0027232

申请日：2000-11-07

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES S ,  GEISS PETER J ,  GRAY PETER B ,  HARAME DAVID L ,  SCHONENBERG KATHRYN T ,  ST ONGE STEPHEN A ,  SUBBANNA SESHADRI

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.