公开(公告)号：GB1236339A

公开(公告)日：1971-06-23

申请号：GB1401369

申请日：1969-03-18

Applicant: IBM

Inventor： SCHUENEMANN CLAUS HEINRICH

IPC: G06F7/00 ,  H03K19/0185 ,  H03K19/173 ,  H03K19/177

Abstract: 1,236,339. Logical function generators. INTERNATIONAL BUSINESS MACHINES CORP. 18 March, 1969 [19 March, 1968], No. 14013/69. Heading G4A. In a variable logical function generator, the AND function of the contents of simultaneously addressed bit stores is supplied to a logic unit having a plurality of gated electrical paths, the gating devices being operable in different combinations to generate respective logical functions of the contents of the addressed stores. In Figs. 1a, 1b bit stores 61 1 ... 61 n , 62 1 ... 62 n are addressed by respective rows XA of the diode matrix shown when connected columns of the matrix are energized by a programming ring AS. Initially, inputs E1 ... Em (top left, Fig. 1a) are loaded into the bit stores under control of the first two stages of the ring (for values 1 and 0 respectively), rows XA addressing the bit stores into which the value is to be loaded under control of gates 78, 85, and rows XE, XR of the matrix providing the writing current via ORs 80, 81, 82. The ring then energizes a series of YL and corresponding YS columns of the matrix in turn. Each YL column energized addresses selected bit stores via rows XA and produces selected gating signals f 1 , f 1 1 , f 2 , f 2 1 , f 3 , # 3 1 from like-labelled matrix rows to, control selected gates 65, 67, 69, 71, 73, 75 in a logic unit LV. The addressed bit stores 61 1 ... 61 n provide their inverse outputs to a line 63 which effectively ORs them, the result being inverted at 66 to give the AND of the addressed bit store 61 1 ... 61 n contents. An identical facility is provided for the bit stores 62 1 ... 62 n . These AND functions, and their inverses (from lines 63, 64 direct), are selectively gated at 65, 67, 69, 71 to an OR 68, the output of which is selectively gated at 73, 75 to set or reset a bistable 76, The YS column corresponding to the energized YL column is energized next to address selected bit stores via rows XA and cause, via row XS, the bi-stable 76 state to be gated 88, 89 into the addressed bit stores. After the series of YL, YS energizations, one or more columns YA are energized in turn to extract the stored result(s) via logic unit LV and bi-stable 76 to output AG feeding, e.g. a data processor store.

公开(公告)号：GB1178807A

公开(公告)日：1970-01-21

申请号：GB5498768

申请日：1968-11-20

Applicant: IBM

Inventor： SCHUENEMANN CLAUS HEINRICH

IPC: G11C11/411 ,  H03K3/012 ,  H03K3/013 ,  H03K3/35

Abstract: 1,178,807. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 20 Nov., 1968 [15 Dec., 1967], No. 54987/68. Heading H3T. A bi-stable circuit comprises two doubleemitter four layer transistors with their middle layers cross-coupled, a first emitter of each connected to a common potential source and the other emitters to respective sources of input signals. The collectors may be connected to a common supply resistor. Addressing is effected by changing the potential of the commoned emitters so as to divert current in the conducting transistor to the other emitter. Read-out is effected by detecting current flow in one of the non-commoned emitters and writing is effected raising the emitter potential so as to prevent current-flow. The circuit is compared with a similar known bi-stable circuit comprising cross-coupled conventional double - emitter transistors and individual diode collector loads (Fig. 1, not shown).

公开(公告)号：GB1293442A

公开(公告)日：1972-10-18

申请号：GB1870970

申请日：1970-04-20

Applicant: IBM

Inventor： SCHUENEMANN CLAUS HEINRICH ,  SPRUTH WILHELM GUSTAV

IPC: G06F1/03 ,  G06F7/50 ,  G06F7/505 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F13/12 ,  G06F15/78

Abstract: 1293442 Data processing INTERNATIONAL BUSINESS MACHINES CORP 20 April 1970 [2 May 1969] 18709/70 Addition to 1218407 Heading G4A An electronic data processing system, wherein logic and arithmetic functions are performed by table-look-up operations on stored function tables, comprises at least one read-only function store containing function tables, at least one work store arranged in operation to store operands, and a microprogramme store arranged in operation to emit microinstructions each including an operation code, each function and microprogramme store comprising a read-only store and having a respective decoder arranged to decode a part of the operation code particular to the store. In the CPU, address, data and control buses interconnect two work stores, a main store, the microprogramme read-only store and a branch read-only store for it, and readonly function stores (for binary addition, shift, ORing, EXCL-ORing, and inversion). Arrays of read-only function stores feeding each other are disclosed. The branch store evaluates (b#c)#a, and uses it as part of the next microinstruction address, the rest coming from the current microinstruction. Here a, b, c are 4-bits each, and come from the current microinstruction, the address bus and the data bus respectively. Address, data and control buses interconnect the CPU with I/O controllers each of which has two work stores, arithmetic and logic arrangements and a function control, similarly to the CPU. Requests for access to the buses from the CPU and I/O controllers, if concurrent, are resolved using a priority table in a readonly store. The CPU and I/O controllers communicate with each other via respective reserved areas in main store. Error correction Hamming code generators (using tables in read-only stores) are provided for the inputs and outputs of the CPU work stores. Multiplication is by examining the multiplier bits in turn using a mask, a 1 bit causing the multiplicand to be added into a result field, and in either case the multiplicand and multiplier then being shifted one place left and right respectively.

公开(公告)号：GB1253763A

公开(公告)日：1971-11-17

申请号：GB6305969

申请日：1969-12-29

Applicant: IBM

Inventor： BERGER HORST HEINZ ,  WIEDMANN SIEGFRIED KURT ,  SCHUENEMANN CLAUS HEINRICH

IPC: G11C11/411 ,  G11C15/00 ,  H01L21/00 ,  H01L27/00 ,  H01L27/07 ,  H01L27/082 ,  H01L27/10 ,  H01L27/102 ,  H03K3/286 ,  H03K3/288 ,  H03K3/35

Abstract: 1,253,763. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINE CORP. 29 Dec., 1969 [30 Dec., 1968 (2); 31 Dec., 1968], No. 63059/69. Heading H3T. [Also in Divisions G4 and H1] A monolithic data storage cell has crosscoupled bipolar transistors T1, T2 with loads 10, 20 formed by controllable semi-conductor current sources, such as transistors of opposite type to T1, T2. The cell is selected by a pulse on a word line V2, and information is written in by lowering the emitter voltage of an appropriate one of a further pair of transistors T 3 , T 4 by means of bit lines B0, B1. Information is read out by a differential amplifier (not shown) detecting which of T3, T4 supplies the greater current upon selection of the cell (by V2). Alternatively, the cell may be selected by a positive pulse to the common emitter of 10, 20 (Fig. 12A, not shown) the bit lines being connected to the separate emitters of T1, T2, and the transistors T3, T4 being dispensed with. A further address signal may be applied to the commoned bases of 10, 20, enabling threedimensional matrix operation (Fig. 13A, not shown). The cross-coupled portion T1, T2 of Fig. 4 (Fig. 6A, not shown) and the remaining portion (Fig. 5A, not shown) are integrated (Figs. 6B, 6C and 5A, 5B, not shown) in separate portions of a monolith; and a matrix of the cells (Fig. 7, not shown) is described, the word line therein being in the co-called sub-collector and epitaxial layer of the isolated zone housing T1 and T2. The transistors T1, T2 are formed to operate inversely to the rest, so that space saving is achieved. The Fig. 4 circuit (also Fig. 8A, not shown) may be operated with V N and V 2 connected, and a more economical integrated layout used (Fig. 8B, not shown) for each cell, a matrix of which is described (Figs. 9A, 9B and 10, not shown). In Fig. 11 (not shown) a p + diffusion of low resistance replaces the metallized word line of Fig. 10 (not shown).

公开(公告)号：GB1248273A

公开(公告)日：1971-09-29

申请号：GB1665669

申请日：1969-03-31

Applicant: IBM

Inventor： LOUIS HELMUT PETER ,  SCHUENEMANN CLAUS HEINRICH ,  SPRUTH WILHELM

IPC: G11C11/41 ,  G11C11/36 ,  G11C11/39 ,  G11C11/411 ,  H03K3/012 ,  H03K3/35

Abstract: 1,248,273. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 31 March, 1969 [30 March, 1968], No. 16656/69. Heading G4C. During read or write operations in a data store, a relatively high power voltage is supplied to the addressed storage elements and the voltage supply to each unaddressed element is interrupted, whereas at other times a relatively low standby voltage is supplied to all the elements. In the matrix thyristor or SCR store of Fig. 1, the voltages referred to are applied between row and column leads X, Y. Row leads B0, B1 are used for bits to be written or being non-destructively sensed. A second embodiment uses single-emitter thyristors, leads X being dispensed with, their function being taken over by the bit leads, B0, B1. Power consumption in the matrix is the same during and between read and write operations. Monolithic construction is mentioned.