公开(公告)号：US3900838A

公开(公告)日：1975-08-19

申请号：US44570074

申请日：1974-02-25

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/40

CPC classification number: G11C11/412 ,  H01L27/11

Abstract: A semiconductor storage cell operating on the flip flop principle and in which the cross-coupled storage transistors and the load transistors are field effect and bipolar transistors, respectively. The semiconductor cell is a FET storage cell whose active storage transistors are field effect transistors which, in contrast to bipolar transistors, do not have to be isolated against each other, thus occupying a smaller semiconductor area. The bipolar load transistors permit a very low stand-by current on the order of the leakage current to be impressed, which in contrast to FET load elements can be changed to a desirably high operating current during reading. Apart from this, the bipolar transistors in the load branches need not be isolated against each other in this configuration, so that at a low rate of permanent power dissipation, which is roughly comparable to that of CMOS storages, the semiconductor cell area can be further reduced.

公开(公告)号：IT1151018B

公开(公告)日：1986-12-17

申请号：IT2302180

申请日：1980-06-26

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED KURT

IPC: G11C11/41 ,  G05F3/20 ,  G05F3/22 ,  G11C7/00 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L21/8229 ,  H01L27/102 ,  G11C

Abstract: Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and the impedance converter to the storage array. The reference voltage generating circuit includes a current source and at least one reference storage cell identical in construction to the storage cells of the array. The reference voltage generating circuit provides a reference voltage to the impedance converter which supplies a second reference voltage to the array at a greatly reduced impedance. The equivalent circuit of the storage cells is that of a capacitor in parallel with a diode. Thus, the impedance converter provides an initial surge of capacitive current which restores the cells, followed by a standby current which is a function of the diode characteristics of the cell equivalent circuit.

公开(公告)号：IT8023021D0

公开(公告)日：1980-06-26

申请号：IT2302180

申请日：1980-06-26

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED KURT

IPC: G11C11/41 ,  G05F3/20 ,  G05F3/22 ,  G11C7/00 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L21/8229 ,  H01L27/102 ,  G11C

Abstract: Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and the impedance converter to the storage array. The reference voltage generating circuit includes a current source and at least one reference storage cell identical in construction to the storage cells of the array. The reference voltage generating circuit provides a reference voltage to the impedance converter which supplies a second reference voltage to the array at a greatly reduced impedance. The equivalent circuit of the storage cells is that of a capacitor in parallel with a diode. Thus, the impedance converter provides an initial surge of capacitive current which restores the cells, followed by a standby current which is a function of the diode characteristics of the cell equivalent circuit.

公开(公告)号：AU3515271A

公开(公告)日：1973-05-03

申请号：AU3515271

申请日：1971-10-29

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  HO IRVING TZE ,  JEN TEH-SEN ,  PRICER WILBUR DAVID ,  WIEDMANN SIEGFRIED KURT

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/07 ,  H01L27/102 ,  G11C11/40

Abstract: This specification discloses a stored charge storage cell for monolithic memories. The cell comprises a device akin to a silicon-controlled rectifier and can be schematically illustrated as an NPN and a PNP transistor connected together in what is commonly called a hook circuit. A fixed potential is applied to the semiconductor zone of the device not commonly used as a terminal for a silicon-controlled rectifier so that the cell is prevented from latching as a silicon-controlled rectifier or hook circuit would normally latch. The charge on the capacitance of collector-base PN junctions of the NPN and PNP transistors is then controlled to store data in the cell.

公开(公告)号：GB1281808A

公开(公告)日：1972-07-19

申请号：GB2643371

申请日：1971-04-19

Applicant: IBM

Inventor： LOHREY FRED HELMUT ,  WIEDMANN SIEGFRIED KURT

IPC: G11C15/04

Abstract: 1281808 Transistor bi-stable circuits INTERNATIONAL BUSINESS MACHINES CORP 19 April 1971 [20 April 1970] 26433/71 Heading H3T [Also in Division G4] Each cell of an associative storage array comprises a pair of cross-coupled transistors T1, T2 and a pair of input/output transistors T3, T4 connected as shown. A further pair of load transistors T5, T6 of conductivity opposite type to transistors T1, T2 may be provided between points A, B and a control voltage source V 1 . In a normal read operation, the potential of word line W/L is raised so that the transistor T3 or T4 with its base connected to that of the conducting transistor T2 or T1 conducts to provide an output on the B 1 or B0 bit line, the transistors T3, T4 being held non-conductive while the cell is not being accessed. In a write operation, the potential of the B0 or B1 bit line is decreased while that of the word line is raised to cause T3 or T4 to conduct and reduce the potential at point A or B until the transistor T1 or T2 with its base connected to that point is biased off and the other transistor T2 or T1 on. To perform associative read-out, the potential of bit line B0 or B1 is lowered to approximately that of the word line. If the cell is in the "1" state with T2 on, and a search for a "0" bit is made by lowering the potential of bit line B1, T3 conducts to cause current flow in the associative sense line A/S which is detected as a mismatch by amplifier 28. If the cell is in the "O" state with T1 on, T3 does not conduct, and if all cells connected to common line A/S similarly indicate matching conditions, a match output is obtained from amplifier 28. Voltage V1 may be varied to make the resistance of the cell very low so that read and write operations can be made rapidly with low power dissipation.

公开(公告)号：IT1149955B

公开(公告)日：1986-12-10

申请号：IT2191380

申请日：1980-05-09

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: H03K17/66 ,  H03K19/013 ,  H03K19/082 ,  H03K

Abstract: Bipolar logic circuits such as inverters and NAND circuits are disclosed which are of extremely low DC power dissipation and very high speed. The basic circuit is an inverter circuit which incorporates at least a single switchable transistor (3). The emitter (6) of the NPN transistor (3) is connected to a potential level which may be ground while the collector is connected via a load device, a resistor or a complementary PNP transistor (2), to a positive power supply potential. The base (8) of the NPN transistor (3) is connected to a source (10) of standby current and via a parallel combination of a capacitor (14) and diode (12) to an input terminal (15). When the NPN transistor (3) is switched OFF by the application of a negatively going signal, standby current from the current source (10) is switched to ground via the diode (12) which has a lower switching point than the emitter-base diode of the NPN transistor. The capacitor (14) in parallel with the diode, is charged during this period so that when a positive going transient is applied at the input, the diode is backward-biased and the transient is applied along with the standby current to the base (8) of the NPN transistor, switching it to the conducting or ON state. … In addition to the basic logic circuit, a two-input NAND circuit which includes a pair of PNP bipolar transistors and a pair of NPN bipolar transistors disclosed.

公开(公告)号：DE3062604D1

公开(公告)日：1983-05-11

申请号：DE3062604

申请日：1980-06-03

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: H03K17/66 ,  H03K19/013 ,  H03K19/082 ,  H03K17/74

Abstract: Bipolar logic circuits such as inverters and NAND circuits are disclosed which are of extremely low DC power dissipation and very high speed. The basic circuit is an inverter circuit which incorporates at least a single switchable transistor (3). The emitter (6) of the NPN transistor (3) is connected to a potential level which may be ground while the collector is connected via a load device, a resistor or a complementary PNP transistor (2), to a positive power supply potential. The base (8) of the NPN transistor (3) is connected to a source (10) of standby current and via a parallel combination of a capacitor (14) and diode (12) to an input terminal (15). When the NPN transistor (3) is switched OFF by the application of a negatively going signal, standby current from the current source (10) is switched to ground via the diode (12) which has a lower switching point than the emitter-base diode of the NPN transistor. The capacitor (14) in parallel with the diode, is charged during this period so that when a positive going transient is applied at the input, the diode is backward-biased and the transient is applied along with the standby current to the base (8) of the NPN transistor, switching it to the conducting or ON state. … In addition to the basic logic circuit, a two-input NAND circuit which includes a pair of PNP bipolar transistors and a pair of NPN bipolar transistors disclosed.

公开(公告)号：AU8419282A

公开(公告)日：1982-12-09

申请号：AU8419282

申请日：1982-05-26

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: G11C11/411 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8229 ,  H01L27/082 ,  H01L27/102 ,  G11C7/02 ,  G11C11/40

Abstract: A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results in a signal path with reduced series resistance and thus higher signals and a faster read operation obtainable. The density is additionally increased by using in common the primary injectors and the bit line injectors of adjacent cells of the array.

公开(公告)号：AU549916B2

公开(公告)日：1986-02-20

申请号：AU8419282

申请日：1982-05-26

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: G11C11/411 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8229 ,  H01L27/082 ,  H01L27/102 ,  G11C7/02 ,  G11C11/40

Abstract: A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results in a signal path with reduced series resistance and thus higher signals and a faster read operation obtainable. The density is additionally increased by using in common the primary injectors and the bit line injectors of adjacent cells of the array.

公开(公告)号：DE3064247D1

公开(公告)日：1983-08-25

申请号：DE3064247

申请日：1980-06-24

Applicant: IBM

Inventor： FETH GEORGE CLARENCE ,  NING TAK HUNG ,  TANG DENNY DUAN-LEE ,  WIEDMANN SIEGFRIED KURT ,  YU HWA NIEN

IPC: H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L21/82

Abstract: Self-aligned semiconductor circuits and process for manufacturing the circuits in which a plurality of transistors (206, 208, 240; 206, 208, 242) is provided, the collector regions/contacts (240, 228; 242, 228) and the base regions/contacts (254, 252; 256, 252) being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors (240, 242) of these transistors can be butted to a recessed field oxide (214) to reduce the extrinsic base area and to minimize excess charge storage in the base region (208). The base contacts, whether polysilicon or metal, etc., provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow.