1.
    发明专利
    未知

    公开(公告)号:DE69019822D1

    公开(公告)日:1995-07-06

    申请号:DE69019822

    申请日:1990-06-27

    Applicant: IBM

    Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.

    2.
    发明专利
    未知

    公开(公告)号:DE69019822T2

    公开(公告)日:1995-12-14

    申请号:DE69019822

    申请日:1990-06-27

    Applicant: IBM

    Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.

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