公开(公告)号：EP1366512A4

公开(公告)日：2009-07-08

申请号：EP01987440

申请日：2001-12-19

Applicant: IBM

Inventor： WALKER GEORGE F ,  GOLDBLATT RONALD D ,  GRUBER PETER A ,  HORTON RAYMOND R ,  PETRARCA KEVIN S ,  VOLANT RICHARD P ,  CHENG TIEN-JEN

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48

CPC classification number: H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract translation: 描述了用于形成适用于引线键合和焊料凸点倒装芯片连接（例如可控塌陷芯片连接（C4））的公共输入 - 输出（I / O）位置的过程。 本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易因结合力而损坏。 本发明通过在衬垫的顶表面上提供具有贵金属的部位，同时提供扩散阻挡层以维持金属互连的高导电性，从而降低了损坏的风险。 通过提供在衬底中形成的特征中选择性地沉积金属层的方法来减少用于在衬底内形成I / O部位的工艺步骤。 由于本发明的I / O站点可以用于引线键合或焊料凸点连接，这为芯片互连选项提供了增加的灵活性，同时还降低了工艺成本。

公开(公告)号：EP1461828A4

公开(公告)日：2005-09-28

申请号：EP02803310

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

CPC classification number: B81C1/00246 ,  B81B2201/016 ,  B81B2201/018 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0122 ,  B81C2203/0735 ,  H01G5/40 ,  H01H59/0009

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：EP2020023A4

公开(公告)日：2012-09-19

申请号：EP07761307

申请日：2007-04-26

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

公开(公告)号：EP1668745A4

公开(公告)日：2008-12-03

申请号：EP03770552

申请日：2003-09-30

Applicant: IBM

Inventor： VOLANT RICHARD P ,  PETRARCA KEVIN S ,  WALKER GEORGE F

IPC: H01R12/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5387 ,  H01L24/18 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A three-dimensional package consisting of a plurality of folded integrated circuit chips ( 100, 110, 120 ) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( 130 ) is provided with additional interconnect wiring to a substrate ( 500 ), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.

公开(公告)号：EP1800335A4

公开(公告)日：2008-01-02

申请号：EP05797431

申请日：2005-09-20

Applicant: IBM

Inventor： PETRARCA KEVIN S ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL ,  RODBELL KENNETH P

IPC: H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76877

Abstract: Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer (440). The impure copper seed layer (440) covers a barrier layer (230), which covers an insulating layer (115) that has an opening. Electroplated copper fills the opening in the insulating layer (115). Through a chemical mechanical polish, the barrier layer (230), the impure copper seed layer (440) derived from an electroplated copper bath, and the electroplated copper are planarized to the insulating layer (115).

公开(公告)号：WO2011090912A3

公开(公告)日：2011-11-03

申请号：PCT/US2011021446

申请日：2011-01-17

Applicant: IBM ,  VOLANT RICHARD P ,  FAROOQ MUKTA G ,  PETRARCA KEVIN S

Inventor： VOLANT RICHARD P ,  FAROOQ MUKTA G ,  PETRARCA KEVIN S

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/48

CPC classification number: H01L21/76879 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/29 ,  H01L24/82 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/29 ,  H01L2224/29298 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A microelectronic assembly and method of forming a through hole extending through a first and second wafer are provided. The first and second wafer have confronting faces and metallic features at the faces which are joined together to assemble the wafers. A hole can be etched through the first wafer until a gap is exposed between the confronting faces. The hole can have a first wall and a second wall sloping inwardly from the first wall to an opening through which the gap is exposed. Material of the first or second wafers exposed within the hole can then be sputtered creating a wall between the confronting faces. The hole can be etched so as to extend the first wall through the first wafer, such that the wall of the hole extends continuously from the first wafer into the second wafer. An electrically conductive through silicon via can then be formed.

Abstract translation: 提供了一种形成延伸穿过第一和第二晶片的通孔的微电子组件和方法。 第一和第二晶片在表面上具有相对的面和金属特征，这些面连接在一起以组装晶片。 可以通过第一晶片蚀刻孔，直到在相对的面之间暴露间隙。 该孔可具有第一壁和第二壁，该第一壁和第二壁从第一壁向内倾斜至间隙暴露的开口。 暴露在孔内的第一或第二晶片的材料然后可被溅射，从而在相对的面之间形成壁。 该孔可以被蚀刻以使第一壁延伸穿过第一晶片，使得孔的壁从第一晶片连续地延伸到第二晶片中。 然后可以形成导电的硅通孔。

公开(公告)号：JP2005057264A

公开(公告)日：2005-03-03

申请号：JP2004218340

申请日：2004-07-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG TIEN-JEN ,  EICHSTADT DAVID E ,  GRIFFITH JONATHAN H ,  KNARR RANDOLPH F ,  PETRARCA KEVIN S ,  QUON ROGER A

IPC: H01L21/60 ,  H01L21/44 ,  H01L23/48 ,  H05K3/34 ,  H05K3/40

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/03622 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H05K3/3457 ,  H05K3/4007 ,  H01L2224/05099

Abstract: PROBLEM TO BE SOLVED: To provide a method for producing fine pitch electric conduction pads for flip chip bonding (also referred to as bumps). SOLUTION: Solder bumps which connect an electron device with a substrate or another structure are formed, by plating copper pins of high aspect ratio on a supporting structure, enclosing the pins into barrier materials, plating over the barrier materials with solders, and then, reflowing the solders. This electric structure includes electrical connection members fitted so as to connect with another electric structure. The structure comprises a set of contacts in the electric structure, at least one interface layer attaching to the set of contacts, a set of pads which are disposed on the set of contacts and include the interface layer, a set of electric conduction pins directly attaching to the pads, barrier layers attaching to all exposure surfaces of the set of the pins, and solder layers which enclose the barrier layers. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造用于倒装芯片接合的细间距导电焊盘的方法（也称为凸块）。 解决方案：通过在支撑结构上镀覆高纵横比的铜销将电子器件与衬底或其他结构连接起来的焊料凸块，将引脚封装成阻挡材料，用焊料覆盖阻隔材料，以及 然后，回流焊接。 这种电气结构包括电连接构件，其被安装成与另一个电气结构连接。 该结构包括在电结构中的一组触点，至少一个界面层，附着到该组触点，一组焊盘，它们设置在触点组上，并包括界面层，一组导电引脚直接连接 连接到该组引脚的所有暴露表面的焊盘，阻挡层以及围绕阻挡层的焊料层。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004025431A

公开(公告)日：2004-01-29

申请号：JP2003065512

申请日：2003-03-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： VOLANT RICHARD P ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  DAVID M ROCKWELL ,  STEIN KENNETH JAY

IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  B81C99/00 ,  H01H59/00

CPC classification number: H01H59/0009 ,  B81B3/0021 ,  B81B2201/018 ,  B81B2203/058 ,  B81B2207/015 ,  B81C1/00214 ,  H01H2001/0068 ,  H01H2059/0054

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor torsional micro-electromechanical (MEM) switch which has a control electrode being almost perpendicular to a switching electrode, applies an electrical separation between the control signal and a switch signal, is equipped with a plurality of control parts for opening/closing switches, and whole switching area arranged in various multiple-pole, multiple-throw is remarkably reduced.
SOLUTION: The switch is equipped with a conductive movable control electrode 50 and an insulated semiconductor torsion beam 60 attached to the movable control electrode, the insulated torsion beam and the movable control electrode being parallel to each other, and a movable contact 20 attached to the insulated torsion beam, wherein the combination of the insulated torsion beam and the control electrode is perpendicular to the movable contact. The torsional MEM switch has the control electrodes almost perpendicular to the switching electrodes. The MEM switch has a plurality of control parts to activate the device to form a single-pole, single-throw switch or a multiple-pole, multiple-throw switch. The manufacturing method of the torsional MEM switch is completely compatible with the CMOS manufacturing process.
COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2012096909A3

公开(公告)日：2013-01-17

申请号：PCT/US2012020704

申请日：2012-01-10

Applicant: IBM ,  FAROOQ MUKTA G ,  GRAVES-ABE TROY L ,  HANNON ROBERT ,  KINSER EMILY R ,  LANDERS WILLIAM F ,  PETRARCA KEVIN S ,  VOLANT RICHARD P ,  WINSTEL KEVIN R

Inventor： FAROOQ MUKTA G ,  GRAVES-ABE TROY L ,  HANNON ROBERT ,  KINSER EMILY R ,  LANDERS WILLIAM F ,  PETRARCA KEVIN S ,  VOLANT RICHARD P ,  WINSTEL KEVIN R

IPC: H01L21/027

CPC classification number: H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8385 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2224/83

Abstract: A method of forming alignment marks in three dimensional (3D) structures and corresponding structures are disclosed. The method includes forming apertures (126) in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate (116); and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

Abstract translation: 公开了一种在三维（3D）结构和对应结构中形成对准标记的方法。 该方法包括在第一半导体衬底的第一表面中形成孔（126）; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上减薄第一半导体以提供孔和第一半导体衬底（116）之间的光学对比度。 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

公开(公告)号：WO2011119308A3

公开(公告)日：2011-12-29

申请号：PCT/US2011026957

申请日：2011-03-03

Applicant: IBM ,  FAROOQ MUKTA G ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

Inventor： FAROOQ MUKTA G ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L21/6835 ,  H01L23/3128 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/00

Abstract: A temporary substrate (901) having an array of first solder pads (192) is bonded to the front side of a first substrate (101) by reflowing an array of first solder balls (250). The first substrate (101) is thinned by removing the back side, and an array of second solder pads (142) is formed on the back side surface of the first substrate (101). The assembly of the first substrate (101) and the temporary substrate (901) is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip (100) and a handle portion (900). A second semiconductor chip (200) is bonded to an assembly through an array of the second solder balls (150). The handle portion (900) is removed from each assembly by reflowing the array of the first solder balls (250), while the array of the second solder balls (150) does not refiow. The assembly is subsequently mounted on a packaging substrate (300) employing the array of the first solder balls (250).

Abstract translation: 具有第一焊盘（192）的阵列的临时衬底（901）通过回流第一焊球（250）的阵列而接合到第一衬底（101）的前侧。 通过去除背面而使第一衬底（101）变薄，并且在第一衬底（101）的背侧表面上形成有第二焊盘（142）的阵列。 切割第一基板（101）和临时基板（901）的组装以形成多个堆叠，每个堆叠包括第一半导体芯片（100）和手柄部分（900）的组件。 第二半导体芯片（200）通过第二焊球（150）的阵列结合到组件。 通过回流第一焊球（250）的阵列，而第二焊球（150）的阵列不反射，从每个组件移除手柄部分（900）。 随后，使用第一焊球（250）的阵列将组件安装在包装衬底（300）上。