公开(公告)号：JP2007150298A

公开(公告)日：2007-06-14

申请号：JP2006310984

申请日：2006-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RATH DAVID L ,  CHIN CHAO YANG ,  SHOM PONOTH ,  WONG KEITH KWONG HON

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089

Abstract: PROBLEM TO BE SOLVED: To provide a conductor-dielectric structure, and to provide a method for manufacturing the same. SOLUTION: A structure containing a dielectric layer which contains a feature formed by patterning inside it, is prepared for a conductor-dielectric mutual connection structure. A plating seed layer is allowed to stick to the surface of the dielectric layer in the pattern-forming feature. A sacrificial seed layer is allowed to stick to the surface of the plating seed layer in the pattern-forming feature. The thickness of the sacrificial seed layer is reduced by inverse plating. A conductive metal is plated on the surface of the sacrificial seed layer in the pattern-forming feature. In addition, such structure is provided too as contains a dielectric layer comprising the pattern-forming feature inside it, a plating seed layer on the surface of the dielectric layer in the pattern-forming feature, and a discontinuous sacrificial seed layer positioned in the pattern-forming feature. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供导体 - 电介质结构，并提供其制造方法。 解决方案：制备一种包含介电层的结构，其中包含通过在其内部图案形成的特征而形成的特征，用于导体 - 电介质互连结构。 允许电镀种子层在图案形成特征中粘附到电介质层的表面。 允许牺牲种子层在图案形成特征中粘附到电镀种子层的表面。 牺牲种子层的厚度通过反镀减少。 在图案形成特征中，导电金属被电镀在牺牲种子层的表面上。 此外，也提供这样的结构，其包含其内部的图案形成特征的电介质层，在图案形成特征中的电介质层的表面上的电镀种子层和位于图案中的不连续的牺牲种子层 形成特征。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2009302501A

公开(公告)日：2009-12-24

申请号：JP2008260280

申请日：2008-10-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HORAK DAVID VACLAV ,  SHOM PONOTH ,  YANG CHIH-CHAO

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect structure having electromigration resistance enhanced by lining the inside of a lower portion of a via opening inside with a multi-layered liner.
SOLUTION: The multi-layered liner includes, from the patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within the lower portion of the via opening formed within a dielectric material.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有通过用多层衬垫衬里通孔内部的下部的内部而增强的电迁移阻力的互连结构。 解决方案：多层衬垫包括从介电材料的图案化表面向外的扩散阻挡层，多材料层和含金属的硬掩模。 多材料层包括由下面的电介质覆盖层的残留物构成的第一材料层和由下面的金属覆盖层的残留物构成的第二材料层。 本发明还提供一种制造这种互连结构的方法，其包括在介电材料内形成的通孔开口的下部内的多层衬垫。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007194621A

公开(公告)日：2007-08-02

申请号：JP2006348855

申请日：2006-12-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHOM PONOTH ,  CHEN STEVEN SHYNG-TSONG ,  PHIZHIMONS JOHN A ,  SPOONER TERRY A

IPC: H01L23/52 ,  H01L21/288 ,  H01L21/3205

CPC classification number: H01L21/76873 ,  H01L21/7688 ,  H01L2221/1089

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor structure having a plating enhancement layer.
SOLUTION: There is disclosed a method of manufacturing a semiconductor structure comprising: a step for forming an interlayer dielectric (ILD) layer on a semiconductor layer; a step for forming a conductive plating enhancement layer (PEL) on the ILD layer; a step for patterning the ILD and the PEL; a step for depositing a seed layer in the pattern that is formed by the ILD and the PEL; and a step for plating the top of the seed layer with copper. The PEL reduces resistance over an entire wafer, and functions to facilitate copper plating. The PEL is preferably an optically transparent conductive layer.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造具有电镀增强层的半导体结构的方法。 解决方案：公开了一种制造半导体结构的方法，包括：在半导体层上形成层间电介质层（ILD）层的步骤; 用于在ILD层上形成导电电镀增强层（PEL）的步骤; 图案化ILD和PEL的步骤; 用于在由ILD和PEL形成的图案中沉积种子层的步骤; 以及用铜电镀种子层的顶部的步骤。 PEL降低整个晶片的电阻，并且有助于铜电镀。 PEL优选为光学透明导电层。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2013115427A

公开(公告)日：2013-06-10

申请号：JP2012196345

申请日：2012-09-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： THEODORUS EDUARDUS STANDAERT ,  BALASUBRAMANIAN S HARAN ,  CHENG KANGGUO ,  SHOM PONOTH ,  YAMASHITA TENKO ,  SEO SOON-CHEON

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC classification number: H01L29/6681 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a FinFET which is improved in flatness of a gate.SOLUTION: The gate is arranged on a pattern of fins before unnecessary fins are removed. The unnecessary fins can be removed by using a lithography technique, an etching technique, or a combination of them. All or some of the remaining fins can be merged.

Abstract translation: 要解决的问题：提供一种形成FinFET的方法，该FinFET在栅极的平坦度方面得到改善。 解决方案：在不必要的散热片被去除之前，门被布置在鳍状图案上。 可以通过使用光刻技术，蚀刻技术或它们的组合来去除不需要的散热片。 所有或一些剩余的鳍可以合并。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2008277807A

公开(公告)日：2008-11-13

申请号：JP2008102183

申请日：2008-04-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  EDELSTEIN DANIEL C ,  BREYTA GREGORY ,  COLBURN MATTHEW EARL ,  SHOM PONOTH

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces cross-talk between conducting lines for wiring. SOLUTION: A method of forming a cavity in a semiconductor device 300 comprises a step for depositing an anti-nucleating layer 318 on the interior surface of the cavity in an ILD layer of the semiconductor device. This anti-nucleating layer prevents a subsequently-deposited dielectric layer from being formed in the cavity. By preventing the formation of these layers, capacitance is reduced, thereby resulting in improved semiconductor performance. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种减少用于布线的导线之间的串扰的半导体器件。 解决方案：在半导体器件300中形成腔的方法包括在半导体器件的ILD层中的空腔的内表面上沉积抗成核层318的步​​骤。 该防成核层防止在空腔中形成随后沉积的介电层。 通过防止这些层的形成，电容降低，从而提高半导体性能。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：SG2013068614A

公开(公告)日：2014-09-26

申请号：SG2013068614

申请日：2013-09-12

Applicant: GLOBALFOUNDRIES INC ,  IBM

Inventor： RUILONG XIE ,  CHANRO PARK ,  SHOM PONOTH

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

公开(公告)号：GB2517854B

公开(公告)日：2016-08-31

申请号：GB201419746

申请日：2013-03-13

Applicant: IBM

Inventor： BRUCE B DORIS ,  KANGGUO CHENG ,  BALASUBRAMANIAN HARAN ,  ALI KHAKIFIROOZ ,  PRANITA KULKARNI ,  ARVIND KUMAR ,  SHOM PONOTH

IPC: H01L21/762 ,  H01L21/8238