公开(公告)号：DE3578261D1

公开(公告)日：1990-07-19

申请号：DE3578261

申请日：1985-03-21

Applicant: IBM

Inventor： GUILLAUME WALLACE JOSEPH ,  LOUGHRAN JOHN FARLEY ,  ROGOYSKI JAN ,  WEBER EDWARD VICTOR ,  SIMPSON ROBERT ARTHUR

IPC: H01L21/66 ,  G01B21/20 ,  G03F1/44 ,  G03F1/84 ,  H01J37/30 ,  H01L21/027 ,  G03B41/00

Abstract: A method of forming inspection patterns for inspecting a workpiece, e.g., for electron beam inspection of optical photomasks. The inspection patterns (Figure 5E) are formed from the workpiece patterns (Figure 5B) themselves by applying a first positive windage (Figure 5C) to the workpiece patterns, inverting (Figure 5D) the first positive windaged workpiece patterns and applying a second positive windage to the inverted first positive windaged workpiece patterns. The inspection patterns so produced will contain the requisite guard band and the requisite overlap of abutting patterns.

公开(公告)号：DE3567108D1

公开(公告)日：1989-02-02

申请号：DE3567108

申请日：1985-04-17

Applicant: IBM

Inventor： SIMPSON ROBERT ARTHUR

IPC: G01N23/203 ,  G01R19/00 ,  H01J37/304 ,  G01R19/10 ,  G01R19/25

Abstract: An E-beam alignment correction system employing an up-up integration technique. Input signals during each scan period are integrated and digitized then held in respective registers. The value in one register is converted to its negative value then digitally combined with the other value to generate an alignment correction value. This technique eliminates the requirement of positive and negative integrations needed with up-down integration techniques and droop of the sample and hold device as a function of time. A common analog path is used so that errors add out during digital combination of signal values.

公开(公告)号：DE3266126D1

公开(公告)日：1985-10-17

申请号：DE3266126

申请日：1982-04-15

Applicant: IBM

Inventor： PFEIFFER HANS CHRISTIAN ,  SIMPSON ROBERT ARTHUR ,  STICKEL WERNER

IPC: H01L21/66 ,  G01Q30/02 ,  G01R31/02 ,  G01R31/302 ,  G01R31/305 ,  H05K3/46 ,  G01R31/28

Abstract: An electron beam system for non contact testing of three dimensional networks of conductors embedded in dielectric material, specifically detection of open and short circuit conditions. Top to bottom and top to top surface wiring is tested electrically without making physical electrical contact. The system comprises two flood beams and a focus probe beam wih one flood beam located at either side of the specimen. Proper choice of acceleration potentials, beam currents and dwell times of the beams allow alteration of the secondary electron emission from the specimen in such a way that electrical properties of the conductor networks can be measured directly. The difference in secondary electron emission resulting from different surface potentials is detected as a strong signal which allows clear discrimination between uninterrupted and interrupted as well as shorted pairs of conductors. This testing system can be applied to the high speed testing of advanced VLSI packaging substrates as well as to the greensheets, sublaminates, and laminates from which they are fabricated.