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公开(公告)号:GB2493614A
公开(公告)日:2013-02-13
申请号:GB201213214
申请日:2011-05-09
Applicant: IBM
Inventor: ZHANG LIXIN , SPEIGHT WILLIAM
IPC: G06F12/08
Abstract: A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller. If a cache line is not found within the coherence domain, the memory controller accesses the memory to retrieve the cache line.
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公开(公告)号:GB2494578A
公开(公告)日:2013-03-13
申请号:GB201222539
申请日:2011-05-25
Applicant: IBM
Inventor: CARTER JOHN BRUCE , ZHANG LIXIN , RAJAMANI KARTHICK , SPEIGHT WILLIAM , ELNOZAHY ELMOOTAZBELLAH NABIL , GHEITH AHMED , HENSBERGEN ERIC VAN
IPC: G06F9/54
Abstract: A method, system, and computer usable program product for fast remote communication and computation between processors are provided in the preferred embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
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