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    RESOURCE ALLOCATION IN VIRTUALIZED ENVIRONMENTS
    1.
    发明申请
    RESOURCE ALLOCATION IN VIRTUALIZED ENVIRONMENTS 审中-公开
    虚拟化环境中的资源分配

    公开(公告)号：WO2011000748A3

    公开(公告)日：2011-02-24

    申请号：PCT/EP2010058884

    申请日：2010-06-23

    Applicant: IBM ,  IBM UK ,  ELNOZAHY ELMOOTAZBELLAH NABIL ,  SPEIGHT WILLIAM EVAN ,  ZHANG LIXIN ,  RAJAMONY RAMAKRISHNAN

    Inventor： ELNOZAHY ELMOOTAZBELLAH NABIL ,  SPEIGHT WILLIAM EVAN ,  ZHANG LIXIN ,  RAJAMONY RAMAKRISHNAN

    IPC: G06F9/455 ,  G06F9/50

    CPC classification number: G06F9/50 ,  G06F9/455 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5061 ,  G06F13/00

    Abstract: A method, a system, an apparatus, and a computer program product for allocating resources of one or more shared devices to one or more partitions of a virtualization environment within a data processing system. At least one user defined resource assignment is received for one or more devices associated with the data processing system. One or more registers, associated with the one or more partitions are dynamically set to execute the at least one resource assignment, whereby the at least one resource assignment enables a user defined quantitative measure (number and/or percentage) of devices to operate when the one or more transactions are executed via the partition. The system enables the one or more devices to execute one or more transactions at a bandwidth/capacity that is less than or equal to the user defined resource assignment and minimizes performance interference among partitions.

    Abstract translation: 一种用于将一个或多个共享设备的资源分配给数据处理系统内的虚拟化环境的一个或多个分区的方法，系统，装置和计算机程序产品。 接收与数据处理系统相关联的一个或多个设备的至少一个用户定义的资源分配。 与所述一个或多个分区相关联的一个或多个寄存器被动态地设置为执行所述至少一个资源分配，由此所述至少一个资源分配能够使用户定义的定量量度（数量和/或百分比） 一个或多个事务通过分区执行。 该系统使得一个或多个设备能够以小于或等于用户定义的资源分配的带宽/容量执行一个或多个事务并且使分区之间的性能干扰最小化。

    Processor with branch target address cache and data processing method
    2.
    发明专利
    Processor with branch target address cache and data processing method 有权
    具有分支目标地址高速缓存和数据处理方法的处理器

    公开(公告)号：JP2009048633A

    公开(公告)日：2009-03-05

    申请号：JP2008207408

    申请日：2008-08-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： LEVITAN DAVID S ,  SPEIGHT WILLIAM E ,  ZHANG LIXIN

    IPC: G06F9/38

    CPC classification number: G06F9/3804 ,  G06F9/3844

    Abstract: PROBLEM TO BE SOLVED: To provide a processor with a branch target address cache and a data processing method.
    SOLUTION: An instruction sequencing logic 13 for fetching instructions from a memory system 12 comprises a branch logic 36 for outputting predicted branch target addresses for use as instruction fetch addresses. The branch logic 36 comprises a level one branch target address cache (BTAC) and a level two BTAC, and each BTAC entry associates at least a tag with a predicted branch target address. The branch logic evaluates the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a second clock cycle.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：为处理器提供分支目标地址高速缓存和数据处理方法。 解决方案：用于从存储器系统12获取指令的指令排序逻辑13包括用于输出用作指令获取地址的预测分支目标地址的分支逻辑36。 分支逻辑36包括一级分支目标地址高速缓存（BTAC）和二级BTAC，并且每个BTAC条目将至少一个标签与预测的分支目标地址相关联。 分支逻辑与第一指令获取地址的标签部分并行地评估一级和二级BTAC，以从第一级BTAC获得第一预测分支目标地址，以在第一时钟周期中用作第二指令获取地址;以及 来自第二级BTAC的第二预测分支目标地址，用作第二时钟周期中的第三指令获取地址。 版权所有（C）2009，JPO＆INPIT

    Assigning memory to on-chip coherence domains
    4.
    发明专利
    Assigning memory to on-chip coherence domains 未知

    公开(公告)号：GB2493614A

    公开(公告)日：2013-02-13

    申请号：GB201213214

    申请日：2011-05-09

    Applicant: IBM

    Inventor： ZHANG LIXIN ,  SPEIGHT WILLIAM

    IPC: G06F12/08

    Abstract: A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller. If a cache line is not found within the coherence domain, the memory controller accesses the memory to retrieve the cache line.

    Cache partitioning in virtualized environments
    5.
    发明专利
    Cache partitioning in virtualized environments 未知

    公开(公告)号：GB2485328A

    公开(公告)日：2012-05-09

    申请号：GB201204882

    申请日：2010-08-19

    Applicant: IBM

    Inventor： ZHANG LIXIN ,  LIN JIANG

    IPC: G06F12/08 ,  G06F12/12

    Abstract: A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.

    Zuweisen von Speicher zu chipintegrierten Kohärenz-Domänen
    7.
    发明专利
    Zuweisen von Speicher zu chipintegrierten Kohärenz-Domänen 未知

    公开(公告)号：DE112011100825T5

    公开(公告)日：2012-12-27

    申请号：DE112011100825

    申请日：2011-05-09

    Applicant: IBM

    Inventor： ZHANG LIXIN ,  SPEIGHT WILLIAM EVAN

    IPC: G06F12/08

    Abstract: Es wird ein Mechanismus zum Zuweisen von Arbeitsspeicher zu chipintegrierten Cache-Kohärenz-Domänen bereitgestellt. Der Mechanismus weist Cachespeicher innerhalb einer Verarbeitungseinheit Kohärenz-Domänen zu. Der Mechanismus weist dann den Kohärenz-Domänen Blöcke von Arbeitsspeicher zu. Der Mechanismus überwacht auf Kernen innerhalb der Verarbeitungseinheit laufende Anwendungen und erkennt Anforderungen der Anwendungen. Der Mechanismus kann dann beruhend auf den Anforderungen der in den Kohärenz-Domänen laufenden Anwendungen den Cache-Kohärenz-Domänen Blöcke von Arbeitsspeicher neu zuordnen. Wenn ein Speichercontroller den Cachefehltreffer empfängt, kann der Speichercontroller die Adresse in einer Referenztabelle suchen, in der Cache-Kohärenz-Domänen Blöcke von Arbeitsspeicher zugeordnet sind. An Cachespeicher innerhalb der Kohärenz-Domäne werden Anforderungen zum Durchstöbern gesendet. Wenn in einem Cachespeicher innerhalb der Kohärenz-Domäne eine Cachezeile gefunden wird, wird die Cachezeile durch den die Cachezeile enthaltenden Cachespeicher entweder direkt oder über den Speichercontroller an den Ursprungscache zurückgesendet. Wenn in einem Cachespeicher innerhalb der Kohärenz-Domäne eine Cachezeile nicht gefunden wird, greift der Speichercontroller auf den Arbeitsspeicher zu, um die Cachezeile abzurufen.

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