公开(公告)号：DE3065767D1

公开(公告)日：1984-01-05

申请号：DE3065767

申请日：1980-07-10

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  CAVALIERE JOSEPH RICHARD ,  KONIAN RICHARD ROBERT ,  SRINIVASAN GURUMAKONDA ,  STOLLER HERBERT IVAN ,  WALSH JAMES LEO

IPC: H01L21/033 ,  H01L29/08 ,  H01L29/10 ,  H01L21/00

Abstract: A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.