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    COMPLEMENTARY TRANSISTOR, INVERTING EMITTER FOLLOWER CIRCUIT
    1.
    发明专利
    COMPLEMENTARY TRANSISTOR, INVERTING EMITTER FOLLOWER CIRCUIT 未知

    公开(公告)号：DE3068955D1

    公开(公告)日：1984-09-20

    申请号：DE3068955

    申请日：1980-08-12

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  HENLE ROBERT ATHANASIUS ,  KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

    IPC: H03K19/086 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/66 ,  H03K19/082 ,  H03K19/20

    Abstract: A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the Vbe necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other. In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal. In a logic circuit species of the invention, the emitter of one of the second pair of transistors is connected to the base of the other of the second pair of transistors. NOR logic is performed by connecting additional transistors in parallel with said one of the second pair of transistors, the bases of the additional transistors receiving respective logic input signals. The output from the driver circuit as well as from the logic circuit is derived from the commonly connected emitters of the first pair of transistors. The first pair of transistors conduct only during the transitions of the input signals.

    LARGE SWING DRIVER/RECEIVER CIRCUIT
    3.
    发明专利
    LARGE SWING DRIVER/RECEIVER CIRCUIT 未知

    公开(公告)号：DE3374824D1

    公开(公告)日：1988-01-14

    申请号：DE3374824

    申请日：1983-05-02

    Applicant: IBM

    Inventor： KONIAN RICHARD ROBERT

    IPC: H03K19/086 ,  H03K5/02 ,  H03K19/013 ,  H03K19/018 ,  H03K19/082

    Abstract: Low voltage, low power transistor driver/receiver and logic circuits are disclosed comprising a pair of NPN transistors (1, 2), the base of the first transistor (1) being directly connected to an input terminal (8) and, via a resistor (R o ), to the base of the second transistor (2). A third NPN transistor (3) is connected with the second transistor (2) in series circuit across a low voltage power supply. The junction between the series-connected transistors is coupled to an output terminal (5). A diode (6) is connected between a point on the resistor (R o ) and the collector of the second transistor (2) to prevent saturation. The emitter of the second transistor (2) is connected through a small or zero resistance to one terminal (4) of the power supply. The down level at the output terminal (5) is held by a transistor or diode clamp (7) connected between the base of the third transistor (3) and the other terminal (11) of the power supply.

    COMPLEMENTARY TRANSISTOR EMITTER FOLLOWER CIRCUIT
    5.
    发明专利
    COMPLEMENTARY TRANSISTOR EMITTER FOLLOWER CIRCUIT 未知

    公开(公告)号：DE3062828D1

    公开(公告)日：1983-05-26

    申请号：DE3062828

    申请日：1980-08-12

    Applicant: IBM

    Inventor： KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

    IPC: H03K19/086 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/66 ,  H03K19/013 ,  H03K19/20

    Abstract: An emitter follower series-connected pair of complementary transistors (2,3) provide an output signal at the junction (20) between their commonly connected emitters. The NPN transistor (2) of the pair of transistors (2,3) is directly driven by an input signal applied to its base. The PNP transistor (3) of the pair of transistors (2,3) is driven through a series connection ofa NPN transistor (1) and a Schottky diode (4), the base of the NPN transistor (1) also receiving said input signal. The forward voltage of the Schottky diode (4) is less than the voltage Vbe of the PNP transistor (3). The PNP transistor (3) nominally is held off and conducts only on negative-going input signal transitions to discharge the capacitive load (6). The NPN transistor (2) of the pair of transistors conducts only on positive-going input signal transitions to charge the capacitive load (6). The circuit (14) which has a low power dissipation and a fast response for driving capacitive loads can be extended (15,16) to perform NOR logic and to provide a pair of output signals in phase opposition to each othar.

    6.
    发明专利
    未知

    公开(公告)号：DE2933038A1

    公开(公告)日：1980-05-08

    申请号：DE2933038

    申请日：1979-08-16

    Applicant: IBM

    Inventor： KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

    IPC: H03K17/60 ,  H03K17/66 ,  H03K19/086

    Abstract: A high speed current switch logic circuit wherein a first and a second transistor are operated in a current switching mode and wherein a third and a fourth transistor are provided whereby the current switching operation of the first and second transistor causes current switching operation of the third and fourth transistors and push pull switching of power to a load.

    EMITTER FOLLOWER LOGIC CIRCUIT
    8.
    发明专利
    EMITTER FOLLOWER LOGIC CIRCUIT 未知

    公开(公告)号：DE3066688D1

    公开(公告)日：1984-03-29

    申请号：DE3066688

    申请日：1980-07-10

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  HENLE ROBERT ATHANASIUS ,  KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

    IPC: H03K19/082 ,  H03K19/086 ,  H03K19/013

    Abstract: A high speed, unity gain, emitter follower OR circuit is disclosed including first and second pairs of emitter-connected complementary bipolar transistors with the bases of the NPN transistors being connected together and the bases of the PNP transistors being connected commonly to an input line. One of the NPN transistors id diode-connected (base to collector). The emitter of the other NPN transistor is connected to an output terminal. The input line is connected to the emitters of a pair of OR input NPN transistors and to a first current source. A second current source is coupled to the diode-connected NPN transistor.

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