公开(公告)号：DE3380583D1

公开(公告)日：1989-10-19

申请号：DE3380583

申请日：1983-02-23

Applicant: IBM

Inventor： GAUR SANTOSH PRASAD ,  LECHATON JOHN S ,  SRINIVASAN GURUMAKONDA R

IPC: H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/72

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The biplar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, a portion of the base area (22) wherein the emitter region (34) is planned to be formed is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers (24, 26) with the emitter opening (30) therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter (34) is etched, and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.

公开(公告)号：DE3380431D1

公开(公告)日：1989-09-21

申请号：DE3380431

申请日：1983-02-23

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  DORLER JACK ARTHUR ,  GAUR SANTOSH PRASAD ,  LECHATON JOHN S ,  MOSLEY JOSEPH MICHAEL ,  SRINIVASAN GURUMAKONDA R

IPC: H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H01L29/10 ,  H01L21/82 ,  H01L27/06

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a valuable degree of freedom for design of integrated circuits. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter (34, 35) formation, the base area (22) which is to be the emitter (34) of the selected region havingthe very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitters (34, 35) and rest of the metallization.

公开(公告)号：CA1118536A

公开(公告)日：1982-02-16

申请号：CA326114

申请日：1979-04-23

Applicant: IBM

Inventor： SRINIVASAN GURUMAKONDA R

IPC: C30B25/02 ,  C30B29/06 ,  H01L21/205 ,  H01L21/22 ,  H01L21/74 ,  H01L29/78 ,  H01L21/302

Abstract: EPITA~IAL PROCESS FOR PRODUCING VERY SHARP AUTODOPING PROFILES AND VERY LOW DEFECT DENSITIES ON SUBSTRATES WITH ~IGH CONCENTRATION BURIED IMPURITY LAYERS _ _ A method is described for depositing silicon epitaxy with very low defect levels and sharp dopant profiles which are suitable for fabricating high performance, shallow device structures. The epitaxial layer envisioned is less than about 2 microns in thickness. The layer is deposited upon a silicon substrate that has subcollector buried layers therein of above about 1 x 102 baked at between about 1120 ànd then the epitaxial layer is formed using silicon tetrachloride and a temperature of between about 1000