公开(公告)号：EP1208676A4

公开(公告)日：2008-02-27

申请号：EP00959159

申请日：2000-08-24

Applicant: IBM

Inventor： ALLEN JAMES JR ,  BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  GAUR SANTOSH PRASAD ,  HEDDES MARCO C ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/16 ,  G06F15/177 ,  H04L12/56 ,  H04Q3/00 ,  H04Q3/545 ,  H04J3/24 ,  H04Q11/04

CPC classification number: H04Q3/002 ,  H04L45/742 ,  H04L49/254 ,  H04L49/351 ,  H04L49/354 ,  H04L49/602 ,  H04L2212/00 ,  H04Q3/5455 ,  H04Q2213/1302 ,  H04Q2213/13034 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/13104 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/13322

Abstract: A network switching apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors (12) and a suite of peripheral elements formed on a semiconductor substrate (10). The interface processors (12) and peripherals together form a network processor capable of cooperating with other elements including an optional switch fabric device in executing instructions directing the flow of data in the network.

公开(公告)号：DE60042162D1

公开(公告)日：2009-06-18

申请号：DE60042162

申请日：2000-08-24

Applicant: IBM

Inventor： ALLEN JAMES JR ,  BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  GAUR SANTOSH PRASAD ,  HEDDES MARCO C ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/16 ,  G06F15/177 ,  H04L12/56 ,  H04J3/24 ,  H04Q3/00 ,  H04Q3/545 ,  H04Q11/04

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

公开(公告)号：DE2962031D1

公开(公告)日：1982-03-11

申请号：DE2962031

申请日：1979-04-26

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  GAUR SANTOSH PRASAD ,  POGGE HANS BERNHARD

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/08 ,  H01L29/735 ,  H01L27/08 ,  H01L29/72

Abstract: Lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region are described. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages.

公开(公告)号：DE3380583D1

公开(公告)日：1989-10-19

申请号：DE3380583

申请日：1983-02-23

Applicant: IBM

Inventor： GAUR SANTOSH PRASAD ,  LECHATON JOHN S ,  SRINIVASAN GURUMAKONDA R

IPC: H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/72

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The biplar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, a portion of the base area (22) wherein the emitter region (34) is planned to be formed is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers (24, 26) with the emitter opening (30) therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter (34) is etched, and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.

公开(公告)号：DE3277955D1

公开(公告)日：1988-02-11

申请号：DE3277955

申请日：1982-04-27

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  GAUR SANTOSH PRASAD ,  MAUER IV JOHN LESTER

IPC: H01L29/47 ,  H01L29/872 ,  H01L29/91

公开(公告)号：DE3273921D1

公开(公告)日：1986-11-27

申请号：DE3273921

申请日：1982-06-29

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  GAUR SANTOSH PRASAD

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/401 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/115 ,  H01L27/10 ,  G11C11/24

Abstract: A dynamic memory cell has a P+ injector region (48) surrounded by an N+ region (44) in an N- layer (30) on an N+ layer (20). The injector region (48) is placed between N+ source and drain regions (38, 40). Holes injected into the N-layer (30) are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.

公开(公告)号：HK1069046A1

公开(公告)日：2005-05-06

申请号：HK05102297

申请日：2005-03-15

Applicant: IBM

Inventor： ALLEN JAMES JR ,  BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  GAUR SANTOSH PRASAD ,  HEDDES MARCO C ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/16 ,  G06F15/177 ,  H04L20060101 ,  H04J20060101 ,  H04L12/56 ,  H04Q20060101 ,  H04Q3/00 ,  H04Q3/545

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

公开(公告)号：DE3380431D1

公开(公告)日：1989-09-21

申请号：DE3380431

申请日：1983-02-23

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  DORLER JACK ARTHUR ,  GAUR SANTOSH PRASAD ,  LECHATON JOHN S ,  MOSLEY JOSEPH MICHAEL ,  SRINIVASAN GURUMAKONDA R

IPC: H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H01L29/10 ,  H01L21/82 ,  H01L27/06

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a valuable degree of freedom for design of integrated circuits. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter (34, 35) formation, the base area (22) which is to be the emitter (34) of the selected region havingthe very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitters (34, 35) and rest of the metallization.

公开(公告)号：DE3277998D1

公开(公告)日：1988-02-18

申请号：DE3277998

申请日：1982-06-29

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  EARDLEY DAVID BARRY ,  GAUR SANTOSH PRASAD

IPC: G11C11/34 ,  H01L27/102 ,  H01L27/10

Abstract: A single device dynamic semiconductor memory is formed having a P-type conductivity injector region (72) with high-low-high junctions of N-type conductivity disposed below the injector region. Those junctions trap injected minority charges which are detected by sensing the current flow from a source region (68) to a drain regions (51) which are located on opposite sides of the injector region (72). The source (68) and injector region (72) utilize ohmic contact while the low barrier Schottky contact (80) is made to the drain region (51). In order to provide separation between the depletion region of the Schottky contact (80) and the injector region (72), a heavily doped N (22) region is provided.