公开(公告)号：DE3279917D1

公开(公告)日：1989-10-05

申请号：DE3279917

申请日：1982-06-15

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  MAUER IV JOHN LESTER ,  SARKARY HOMI GUSTADJI

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/306

Abstract: The method comprises blanket depositing a layer of a first material on a semiconductor structure, on the surface of which protruding regions (34A) have been formed bordering with a vertical wall (40) on adjacent areas, and subsequently removing completely or selectively that layer by reactive ion etching where prior to the deposition of said layer the vertical wall (40) is reshaped either by removing material from that wall (40) or by accumulating a second material on said wall (40). The method prevents that uncontrolled residues of materials like a doped polysilicon after reactive ion etching steps. These residues might be detrimental to devices and elements, like transistors and resistors formed in the semi-conductor substrate.

公开(公告)号：DE3070658D1

公开(公告)日：1985-06-20

申请号：DE3070658

申请日：1980-12-12

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L23/532 ,  H01L21/00 ,  H01L21/314

Abstract: A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

公开(公告)号：DE2306994A1

公开(公告)日：1973-11-15

申请号：DE2306994

申请日：1973-02-13

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  DAVIS DONALD EUGENE ,  MARTIN DAVID HUGH

IPC: G11C11/41 ,  G11C5/00 ,  H02J1/00 ,  H03K5/02 ,  H03K17/66 ,  H03K19/086

公开(公告)号：DE3787429D1

公开(公告)日：1993-10-21

申请号：DE3787429

申请日：1987-05-19

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  ECKER MARIO ENRIQUE ,  JONES HARRY JORDAN ,  MALAVIYA SHASHI DHAR

IPC: H01L21/82 ,  G06F1/22 ,  H01L21/822 ,  H01L23/538 ,  H01L27/04 ,  H01L23/52 ,  G06F1/00

公开(公告)号：DE3277955D1

公开(公告)日：1988-02-11

申请号：DE3277955

申请日：1982-04-27

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  GAUR SANTOSH PRASAD ,  MAUER IV JOHN LESTER

IPC: H01L29/47 ,  H01L29/872 ,  H01L29/91

公开(公告)号：DE3273921D1

公开(公告)日：1986-11-27

申请号：DE3273921

申请日：1982-06-29

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  GAUR SANTOSH PRASAD

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/401 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/115 ,  H01L27/10 ,  G11C11/24

Abstract: A dynamic memory cell has a P+ injector region (48) surrounded by an N+ region (44) in an N- layer (30) on an N+ layer (20). The injector region (48) is placed between N+ source and drain regions (38, 40). Holes injected into the N-layer (30) are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.

公开(公告)号：DE2554296A1

公开(公告)日：1976-07-08

申请号：DE2554296

申请日：1975-12-03

Applicant: IBM DEUTSCHLAND

Inventor： BHATIA HARSARAN SINGH ,  O'ROURKE GERALD DENNIS ,  WIEDMANN SIEGFRIED KURT DIPL I

IPC: H01L27/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

公开(公告)号：DE3783672T2

公开(公告)日：1993-07-08

申请号：DE3783672

申请日：1987-05-12

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  JONES HARRY JORDAN ,  MALAVIYA SHASHI DHAR

IPC: H03K19/082 ,  H03K19/086 ,  H03K19/173 ,  H02H3/38 ,  G05F1/20

Abstract: A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs (46,48), while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors (12,22), the collector dotting of their respective reference transistors (55,56), the emitter dotting of one input transistor (12) and a reference transistor (55) to a constant current source (90), the emitter dotting of the other input transistor (22) and the other reference transistor (56) to a different constant current source (100), and an inhibit circuit (72) for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.

公开(公告)号：DE3380613D1

公开(公告)日：1989-10-26

申请号：DE3380613

申请日：1983-11-03

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  RISEMAN JACOB

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/033 ,  H01L21/225 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/00 ,  H01L29/86

Abstract: A high sheet resistance, doped semiconductor resistor is made by a process which produces a resistor diffusion or ion implantation mask having a narrow dimension determined by a "sidewall" technique. The sidewall technique defines the narrow dimension by the thickness of a doped or undoped layer (6) deposited on a different underlying layer having horizontal and vertical surfaces (5). The horizontal portion of the deposited layer is removed by anistropic etching to leave only the vertical portion (6). The vertical portion, if undoped, is removed to define a diffused or ion-implanted resistor. The vertical portion, if doped, may either be removed after heating to form a diffused resistor, or may be left in place to form a resistor in shunt with the diffused resistor.

公开(公告)号：DE2962031D1

公开(公告)日：1982-03-11

申请号：DE2962031

申请日：1979-04-26

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  GAUR SANTOSH PRASAD ,  POGGE HANS BERNHARD

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/08 ,  H01L29/735 ,  H01L27/08 ,  H01L29/72

Abstract: Lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region are described. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages.