公开(公告)号：DE3166340D1

公开(公告)日：1984-10-31

申请号：DE3166340

申请日：1981-10-05

Applicant: IBM

Inventor： CASES MOISES ,  KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWART ,  STAHL WILLIAM LEONARD JR ,  THOMA NANDOR GYORGY

IPC: H01L27/088 ,  H01L27/112 ,  H03K19/0944 ,  H03K19/177

Abstract: A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.