公开(公告)号：DE3376940D1

公开(公告)日：1988-07-07

申请号：DE3376940

申请日：1983-02-01

Applicant: IBM

Inventor： VENESKI GERARD ANTHONY ,  THOMA NANDOR GYORGY ,  CASES MOISES

IPC: H03K19/177 ,  G06F9/22 ,  H03K5/15 ,  G06F9/28

Abstract: A clocking mechanism is provided for multiple overlapped dynamic programmable logic arrays which are used in a digital control unit wherein a sequence of control words are used to produce successive groups of control point signals. Such a control unit includes a plurality of dynamic programmable logic arrays (24-29) for individually producing different ones of the control words. Each such control word includes a strobe field which is coded to identify a programmable logic array other than the one which produced it. The control unit also includes control circuitry (30, 31, 35, 37, 43, 45) responsive to the control words for producing the control point signals for successive machine control cycles. The control circuitry includes circuitry (37, 45) responsive to the strobe field in each control word for producing a strobe signal (Sl, S2, SA, SB, SC or SD) for selecting the next programmable logic array (24-29) to supply a control word to the control circuitry. This control unit further includes clocking circuitry (60) responsive to the strobe signals (S1, S2, SA, etc.) produced by the control circuitry for producing clocking signals (PC1-PC9) for the dynamic programmable logic arrays (24-29). Such clocking circuitry includes only combinatorial logic circuitry for producing the clocking signals.

公开(公告)号：DE3271462D1

公开(公告)日：1986-07-03

申请号：DE3271462

申请日：1982-12-02

Applicant: IBM

Inventor： WYATT VIRGIL DEAN ,  KRAFT WAYNE RICHARD ,  THOMA NANDOR GYORGY

IPC: G06F7/00 ,  G06F9/30 ,  G06F13/40 ,  G06F15/78 ,  G06F13/14

Abstract: The signal transfer mechanism includes a plural-bit data bus (16) formed on an integrated circuit chip for transferring plural-bit binary data signals between plural-bit signal source registers (17, 18, 19, 26, 32, 35) and plural-bit signal destination registers (17, 18, 19, 26, 31, 32, 35) formed on the integrated circuit chip, and which are coupled to the plural-bit data bus (16) for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus and a processor control unit (14) enabling one of the signal source register to put a plural-bit data signal onto the data bus (16) during a first processor control cycle and enabling one of the signal destination registers to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.

公开(公告)号：DE3166340D1

公开(公告)日：1984-10-31

申请号：DE3166340

申请日：1981-10-05

Applicant: IBM

Inventor： CASES MOISES ,  KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWART ,  STAHL WILLIAM LEONARD JR ,  THOMA NANDOR GYORGY

IPC: H01L27/088 ,  H01L27/112 ,  H03K19/0944 ,  H03K19/177

Abstract: A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.

公开(公告)号：DE3478374D1

公开(公告)日：1989-06-29

申请号：DE3478374

申请日：1984-08-01

Applicant: IBM

Inventor： KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWART ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/20 ,  H03K5/02

公开(公告)号：DE2315402A1

公开(公告)日：1973-10-04

申请号：DE2315402D

申请日：1973-03-28

Applicant: IBM

Inventor： RYAN SEN WILLIAM JOHN ,  SCHIRMER EDWARD FRANCIS ,  THOMA NANDOR GYORGY ,  TOLLEY JAMES HOBERT ,  WILDER DONALD LAWRENCE

IPC: H01L21/00 ,  H01L21/683 ,  H01L7/64

Abstract: A system for handling an oriented array of objects, such as integrated circuit chips, includes a fixture in which the chips are held in place by vacuum means. A chip placement tube is capable of reciprocal motion normal to the plane of the fixture to move a chip unidirectionally from its position in the array for placement on a substrate. The system further includes means for positioning a substrate precisely with respect to a chip in the array to allow its direct placement from the array. This fixture and system allows the precise orientation and alignment of semiconductor chips in a wafer to be maintained for laser dicing and chip positioning on a substrate without requiring reorientation. When combined with testing and inspection apparatus and a suitable memory, the system further allows handling and processing of chips to be minimized.

公开(公告)号：DE3373964D1

公开(公告)日：1987-11-05

申请号：DE3373964

申请日：1983-06-16

Applicant: IBM

Inventor： CASES MOISES ,  KRAFT WAYNE RICHARD ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY

IPC: H03K19/096 ,  H03K19/177 ,  H03K19/094 ,  H03K5/15

Abstract: Circuit for speeding up transfers of charges in a Programmed Logic Array structure, formed by FET devices (3) in serially chained charge transfer circuits, comprising a level shifting circuit (21) integrated into bit partitioning stages of the structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings at the inputs of the AND array chains (24) as well as decreasing operational delays of the latter stage, discrete capacitance, (29), added at the output end of the OR array stage (10) for sustaining and reinforcing charge conditions accumulated in that stage prior to readout of that stage, and a source of time related clocking functions (Cp1-Cv3) coupled to stages of the modified structures, with timing relationship selected so as to reduce operational delays of the entire structure while improving its integrity of operation.

公开(公告)号：DE3364802D1

公开(公告)日：1986-09-04

申请号：DE3364802

申请日：1983-02-01

Applicant: IBM

Inventor： KRAFT WAYNE RICHARD ,  CASES MOISES ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY ,  WYATT VIRGIL DEAN

IPC: H01L21/822 ,  G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  H01L21/82 ,  H01L27/04 ,  H03K19/173 ,  H03K19/177

公开(公告)号：DE69311941D1

公开(公告)日：1997-08-14

申请号：DE69311941

申请日：1993-03-26

Applicant: IBM

Inventor： CHEN IMAN PAUL ,  DAVIS JAMES WILLIAM ,  SWANSON ROBERT MARK ,  THOMA NANDOR GYORGY ,  WU DAVID MING-WHEI

IPC: G01R31/28 ,  H03K3/356 ,  H03K19/0948 ,  H03K19/173

Abstract: Disclosed is a basic DCVS (differential cascode voltage switch) tree construct, which can be used as a uniform basis for constructing DCVS logic circuits, register-latch circuits and circuits which can be conditioned individually to function as either or both DCVS logic and register-latches. In addition to logic and load sections that may be identical to corresponding sections of prior art DCVS trees, this construct contains gating elements for providing unique functions of isolation, precharge support and latch input coupling. The isolation function is used to electrically isolate the logic and load sections from each other, so that each section can be made to operate in a mode which is independent of the other section. The precharge support function allows precharging of circuits in the logic section without involvement of the load section. The latch input coupling function allows signals to be applied to and latched in the load section from a source other than the respective logic section. Use of arrays of such trees for constructing complex logic circuits is described.

公开(公告)号：DE3476616D1

公开(公告)日：1989-03-09

申请号：DE3476616

申请日：1984-08-01

Applicant: IBM

Inventor： KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWART ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY

IPC: H03K19/0175 ,  H03K5/02 ,  H03K19/094 ,  H03K19/20 ,  G11C8/00

Abstract: The signal line precharging tristate driver circuit quickly and automatically precharges its off-chip signal line to the desired level just before it switches to its tristate or high impedance output condition. This is accomplished by providing precharge circuitry (10) coupled to the driver circuit (4 through 9) and responsive to the tristate control signal for overriding the normal input data signal and causing the driver circuit to commence charging the signal line. There is further provided tristate circuitry (20, 30, 31, 34, 35, 37, 38, 39) coupled to the driver circuit and responsive to its output voltage level for switching the driver circuit to the high impedance output condition when its output voltage and, hence, the signal line voltage reaches a desired predetermined value.

公开(公告)号：DE3374092D1

公开(公告)日：1987-11-19

申请号：DE3374092

申请日：1983-10-11

Applicant: IBM

Inventor： THOMA NANDOR GYORGY ,  MOORE VICTOR STEWART ,  KRAFT WAYNE RICHARD

IPC: G06F9/22 ,  G06F9/26