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公开(公告)号：DE3478374D1
公开(公告)日：1989-06-29
申请号：DE3478374
申请日：1984-08-01
Applicant: IBM
IPC: H03K19/0175 , H03K19/094 , H03K19/20 , H03K5/02
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公开(公告)号：DE3364296D1
公开(公告)日：1986-08-07
申请号：DE3364296
申请日：1983-02-01
Applicant: IBM
Inventor： KRAFT WAYNE RICHARD , MOORE VICTOR STEWARD , PARKER TONY EDWIN , RHODES JOSEPH CULLEN , STAHL WILLIAM LEONARD , VENESKI GERARD ANTHONY
Abstract: A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.
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3.发明专利
公开(公告)号：DE3265105D1
公开(公告)日：1985-09-05
申请号：DE3265105
申请日：1982-11-23
Applicant: IBM
Inventor： MOORE VICTOR STEWART , KRAFT WAYNE RICHARD , RHODES JOSEPH CULLEN
IPC: H03K19/177 , G06F9/22 , H03M7/00
Abstract: A multi-bit operation code (22) is decoded into a single product term in the AND array (20) of a programmable logic array. That single product term is then processed through a clock (45) driven sequencer (32) to generate a plurality of sequential product term signals. These sequential product terms are decoded by the OR array (30) of the programmable logic array to generate a plurality of sequential time states (58) corresponding to the decoded operation code (22).
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公开(公告)号：DE3369753D1
公开(公告)日：1987-03-12
申请号：DE3369753
申请日：1983-01-28
Applicant: IBM
Inventor： RHODES JOSEPH CULLEN , MOORE VICTOR STUART , KRAFT WAYNE RICHARD , BARRS JOHN WILLIAM
Abstract: The microword generation mechanism includes a first cycle programmable logic array (40) responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction, a second cycle programmable logic array (41) responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction, and at least one additional programmable logic array (42, 43) responsive to the processor instruction to be executed for providing the remainder of the microwords needed to perform the effective address calculations for the operands of the instruction, to fetch the operands from the main storage unit and to execute the operations called for by the instruction.
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公开(公告)号：DE3271462D1
公开(公告)日：1986-07-03
申请号：DE3271462
申请日：1982-12-02
Applicant: IBM
Inventor： WYATT VIRGIL DEAN , KRAFT WAYNE RICHARD , THOMA NANDOR GYORGY
Abstract: The signal transfer mechanism includes a plural-bit data bus (16) formed on an integrated circuit chip for transferring plural-bit binary data signals between plural-bit signal source registers (17, 18, 19, 26, 32, 35) and plural-bit signal destination registers (17, 18, 19, 26, 31, 32, 35) formed on the integrated circuit chip, and which are coupled to the plural-bit data bus (16) for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus and a processor control unit (14) enabling one of the signal source register to put a plural-bit data signal onto the data bus (16) during a first processor control cycle and enabling one of the signal destination registers to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.
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Patent Agency Ranking
公开(公告)号：DE3166340D1
公开(公告)日：1984-10-31
申请号：DE3166340
申请日：1981-10-05
Applicant: IBM
Inventor： CASES MOISES , KRAFT WAYNE RICHARD , MOORE VICTOR STEWART , STAHL WILLIAM LEONARD JR , THOMA NANDOR GYORGY
IPC: H01L27/088 , H01L27/112 , H03K19/0944 , H03K19/177
Abstract: A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.
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公开(公告)号：MX159253A
公开(公告)日：1989-05-09
申请号：MX20043184
申请日：1984-02-23
Applicant: IBM
Inventor： FREEMAN JOSEPH WAYNE , KRAFT WAYNE RICHARD
Abstract: The self-test device for checking drivers (20, 21) circuits connected to a bus, comprises an exclusive - OR circuit (12, 13) associated with each of the drivers (20, 21) for monitoring input signals (I0, I1) to the drivers (20, 21) and output signals (D0, D1) thereof and providing an error signal in the event of a disparity between the input and output signals of the drivers (20, 21). OR circuit (14) is connected to all of the exclusive - OR circuits (12, 13) to sense an error signal from any exclusive - OR circuit (12, 13) and a latch (25) connected to the OR - circuit provides an error indication to inform the system of any failure of the drivers.
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公开(公告)号：DE3373964D1
公开(公告)日：1987-11-05
申请号：DE3373964
申请日：1983-06-16
Applicant: IBM
Inventor： CASES MOISES , KRAFT WAYNE RICHARD , STAHL WILLIAM LEONARD , THOMA NANDOR GYORGY
IPC: H03K19/096 , H03K19/177 , H03K19/094 , H03K5/15
Abstract: Circuit for speeding up transfers of charges in a Programmed Logic Array structure, formed by FET devices (3) in serially chained charge transfer circuits, comprising a level shifting circuit (21) integrated into bit partitioning stages of the structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings at the inputs of the AND array chains (24) as well as decreasing operational delays of the latter stage, discrete capacitance, (29), added at the output end of the OR array stage (10) for sustaining and reinforcing charge conditions accumulated in that stage prior to readout of that stage, and a source of time related clocking functions (Cp1-Cv3) coupled to stages of the modified structures, with timing relationship selected so as to reduce operational delays of the entire structure while improving its integrity of operation.
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9.发明专利
公开(公告)号：DE3364802D1
公开(公告)日：1986-09-04
申请号：DE3364802
申请日：1983-02-01
Applicant: IBM
Inventor： KRAFT WAYNE RICHARD , CASES MOISES , STAHL WILLIAM LEONARD , THOMA NANDOR GYORGY , WYATT VIRGIL DEAN
IPC: H01L21/822 , G06F9/22 , G06F9/26 , G06F9/28 , H01L21/82 , H01L27/04 , H03K19/173 , H03K19/177
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公开(公告)号：DE3476616D1
公开(公告)日：1989-03-09
申请号：DE3476616
申请日：1984-08-01
Applicant: IBM
IPC: H03K19/0175 , H03K5/02 , H03K19/094 , H03K19/20 , G11C8/00
Abstract: The signal line precharging tristate driver circuit quickly and automatically precharges its off-chip signal line to the desired level just before it switches to its tristate or high impedance output condition. This is accomplished by providing precharge circuitry (10) coupled to the driver circuit (4 through 9) and responsive to the tristate control signal for overriding the normal input data signal and causing the driver circuit to commence charging the signal line. There is further provided tristate circuitry (20, 30, 31, 34, 35, 37, 38, 39) coupled to the driver circuit and responsive to its output voltage level for switching the driver circuit to the high impedance output condition when its output voltage and, hence, the signal line voltage reaches a desired predetermined value.
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