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    WIRELESS LAN SUBSCRIBER ADMINISTRATION
    3.
    发明专利
    WIRELESS LAN SUBSCRIBER ADMINISTRATION 未知

    公开(公告)号：AU2003288392A1

    公开(公告)日：2004-07-14

    申请号：AU2003288392

    申请日：2003-11-27

    Applicant: IBM

    Inventor： CREAMER THOMAS EDWARD ,  KATZ NEIL ALAN ,  MOORE VICTOR STEWART

    IPC: H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04W4/00 ,  H04W8/26 ,  H04W12/06 ,  H04W12/08 ,  H04W74/00 ,  H04W84/12 ,  H04W88/16

    Abstract: A method of providing wireless local area network providers with subscriber administration services can include receiving from a processing node in a wireless local area network a request through a gateway interface for approval for a subscriber to access the wireless local area network. The request can specify subscriber identifying information. A determination can be made as to whether the subscriber is approved to access the wireless local area network using the subscriber identifying information by querying a telecommunications subscriber data store. The processing node of the wireless local area network can be notified of the determination results through the gateway interface. If the subscriber is approved, a record of the wireless session can be stored in a session data store.

    MICROWORD CONTROL MECHANISM UTILIZING A PROGRAMMABLE LOGIC ARRAY AND A SEQUENCE COUNTER
    5.
    发明专利
    MICROWORD CONTROL MECHANISM UTILIZING A PROGRAMMABLE LOGIC ARRAY AND A SEQUENCE COUNTER 未知

    公开(公告)号：DE3379917D1

    公开(公告)日：1989-06-29

    申请号：DE3379917

    申请日：1983-02-01

    Applicant: IBM

    Inventor： LEININGER JOEL CALVIN ,  MOORE VICTOR STEWART ,  STAHL WILLIAM L

    IPC: G06F9/22 ,  G06F9/26

    Abstract: A microword control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microword control mechanism includes circuitry (15, 20) responsive to a processor instruction to be executed for providing an instruction dependent signal uniquely representative of such instruction. This microword control mechanism also includes sequence counter circuitry (18) for supplying a sequence of -number signals. This microword control mechanism further includes a programmable logic array (17) responsive to the instruction dependent signal and to the sequence of number signals for producing a sequence of microwords needed to execute the processor instruction.

    A LOGIC PERFORMING CELL FOR USE IN ARRAY STRUCTURES
    6.
    发明专利
    A LOGIC PERFORMING CELL FOR USE IN ARRAY STRUCTURES 未知

    公开(公告)号：DE3166340D1

    公开(公告)日：1984-10-31

    申请号：DE3166340

    申请日：1981-10-05

    Applicant: IBM

    Inventor： CASES MOISES ,  KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWART ,  STAHL WILLIAM LEONARD JR ,  THOMA NANDOR GYORGY

    IPC: H01L27/088 ,  H01L27/112 ,  H03K19/0944 ,  H03K19/177

    Abstract: A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.

    SIGNAL LINE PRECHARGING TRISTATE DRIVE CIRCUIT
    7.
    发明专利
    SIGNAL LINE PRECHARGING TRISTATE DRIVE CIRCUIT 未知

    公开(公告)号：DE3476616D1

    公开(公告)日：1989-03-09

    申请号：DE3476616

    申请日：1984-08-01

    Applicant: IBM

    Inventor： KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWART ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY

    IPC: H03K19/0175 ,  H03K5/02 ,  H03K19/094 ,  H03K19/20 ,  G11C8/00

    Abstract: The signal line precharging tristate driver circuit quickly and automatically precharges its off-chip signal line to the desired level just before it switches to its tristate or high impedance output condition. This is accomplished by providing precharge circuitry (10) coupled to the driver circuit (4 through 9) and responsive to the tristate control signal for overriding the normal input data signal and causing the driver circuit to commence charging the signal line. There is further provided tristate circuitry (20, 30, 31, 34, 35, 37, 38, 39) coupled to the driver circuit and responsive to its output voltage level for switching the driver circuit to the high impedance output condition when its output voltage and, hence, the signal line voltage reaches a desired predetermined value.

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