Method, system and adjustment technology for measuring and saving power in plural time frames
    1.
    发明专利
    Method, system and adjustment technology for measuring and saving power in plural time frames 有权
    方法,系统和调整技术,用于测量和节省大量时间框架中的电力

    公开(公告)号:JP2006197795A

    公开(公告)日:2006-07-27

    申请号:JP2006001813

    申请日:2006-01-06

    CPC classification number: G01V3/08 G06F1/28 G06F1/3203

    Abstract: PROBLEM TO BE SOLVED: To provide a method, a system and an adjustment technology adapted to global system power consumption and power dissipation limit, and responsively controlling power extending over a plurality of time frames. SOLUTION: Power outputs from one or more system power supplies are measured and processed so as to generate power values in a plurality of the different time frames. Measurement values, from the different time frames, are used so as to determine whether the power consumption has to be adjusted in the system. Power from one or more apparatuses is saved, in response to the determination, and the determination compares the maximum threshold, the minimum threshold or both sets with the measured values from the different time frames. The adjustment techniques use a high-precision resistor and a voltage reference controlled current source, and derives voltage drop from the input of a sensing resistor in the power supply; and a common mode voltage is adjusted at a power supply output. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题:提供适用于全球系统功耗和功率耗散极限的方法,系统和调整技术,以及响应地控制在多个时间帧上延伸的功率。 解决方案:测量和处理来自一个或多个系统电源的功率输出,以产生多个不同时间帧中的功率值。 使用来自不同时间帧的测量值来确定系统中是否必须调整功耗。 响应于该确定,保存来自一个或多个装置的电力,并且确定将最大阈值,最小阈值或两组与来自不同时间帧的测量值进行比较。 调节技术使用高精度电阻和参考电压源,并从电源中的感测电阻的输入端导出电压降; 并且在电源输出端调节共模电压。 版权所有(C)2006,JPO&NCIPI

    4.
    发明专利
    未知

    公开(公告)号:DE69908245T2

    公开(公告)日:2004-04-08

    申请号:DE69908245

    申请日:1999-06-24

    Applicant: IBM

    Abstract: A system for monitoring tamper events in a computer system 10 is disclosed. The computer system is on a network. The system comprises a tamper realtime clock (RTC) means 140 which receives at least one tamper event signal from the computer system. The tamper RTC includes a timer 178 for indicating the time of a tamper event and a management device 160 for receiving the at least one tamper event signal. The management device issues a command to the tamper RTC means to obtain the time of the at least one tamper event. The management device also generates a network packet 200 which includes the time of the tamper event to a system administrator of the network. Preferably the computer system has the ability to functionally detect and store the time of a tamper event. A tamper real time clock (RTC) circuit is operatively connected with logic to store the date and time of an event as it occurs. In a preferred embodiment, the tamper event could be as simple as a toggle switch being activated when a cover on the computer system is removed. The computer system also sends network alerts when the cover is removed.

    SYSTEM FOR DETECTING TAMPER EVENTS AND CAPTURING THE TIME FOR THEIR OCCURENCE

    公开(公告)号:CA2271534A1

    公开(公告)日:2000-01-01

    申请号:CA2271534

    申请日:1999-05-12

    Applicant: IBM

    Abstract: A system for monitoring tamper events in a computer system is disclosed. The computer system is on a network. The system comprises a tamper realtime clock (RTC) means which receives at least one tamper event signal from the computer system. The tamper RTC includes a timer for indicating the time of a tamper event and a management device for receiving the at least one tamper event signal. The management device issues a command to the tamper RTC means to obtain the time of the at least one tamper event. The management device also generates a network packet which includes the time of the tamper event to a system administrator of the network. The present invention in a preferred embodiment is directed to a computer system which has the ability to functionally detect and store the time of a tamper event. A tamper real time clock (RTC) circuit is operatively connected with logic to store the date and time of an event as it occurs. In a preferred embodiment, the tamper event could be as simple as a toggle switch being activated when a cover on the computer system is removed. The computer system could also send network alerts when the cover is removed.

    6.
    发明专利
    未知

    公开(公告)号:DE69908245D1

    公开(公告)日:2003-07-03

    申请号:DE69908245

    申请日:1999-06-24

    Applicant: IBM

    Abstract: A system for monitoring tamper events in a computer system 10 is disclosed. The computer system is on a network. The system comprises a tamper realtime clock (RTC) means 140 which receives at least one tamper event signal from the computer system. The tamper RTC includes a timer 178 for indicating the time of a tamper event and a management device 160 for receiving the at least one tamper event signal. The management device issues a command to the tamper RTC means to obtain the time of the at least one tamper event. The management device also generates a network packet 200 which includes the time of the tamper event to a system administrator of the network. Preferably the computer system has the ability to functionally detect and store the time of a tamper event. A tamper real time clock (RTC) circuit is operatively connected with logic to store the date and time of an event as it occurs. In a preferred embodiment, the tamper event could be as simple as a toggle switch being activated when a cover on the computer system is removed. The computer system also sends network alerts when the cover is removed.

    BILATERAL SELECTIVE BURST ERASE SYSTEM FOR GAS PANEL DISPLAYS

    公开(公告)号:CA1071783A

    公开(公告)日:1980-02-12

    申请号:CA265443

    申请日:1976-11-12

    Applicant: IBM

    Abstract: BILATERAL SELECTIVE BURST ERASE SYSTEM FOR GAS PANEL DISPLAYS Erase waveforms effecting improved erase action are provided for a gas panel of the type in which light emitting cells are formed in an ionizable medium at the crossover point of a set of horizontally and vertically extending insulated wires. The erase waveforms include a burst of bipolar pairs of pulses, each pair comprising a low amplitude wide duration erase pulse followed by an opposite polarity narrowed sustain pulse. The burst of pulse pairs being applied during the time frame of a normal sustain operation.

    8.
    发明专利
    未知

    公开(公告)号:FR2331856A1

    公开(公告)日:1977-06-10

    申请号:FR7631444

    申请日:1976-10-11

    Applicant: IBM

    Abstract: Erase waveforms effecting improved erase action are provided for a gas panel of the type in which light emitting cells are formed in an ionizable medium at the crossover point of a set of horizontally and vertically extending insulated wires. The erase waveforms include a burst of bipolar pairs of pulses, each pair comprising a low amplitude wide duration erase pulse followed by an opposite polarity narrowed sustain pulse. The burst of pulse pairs being applied during the time frame of a normal sustain operation.

Patent Agency Ranking