公开(公告)号：JP2011061789A

公开(公告)日：2011-03-24

申请号：JP2010199510

申请日：2010-09-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CRANFORD JR HAYDEN CLAVIE ,  STEVENS JOSEPH MARSH ,  RASMUS TODD MORGAN

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F1/3211 ,  H03F3/45632 ,  H03F2203/45008 ,  H03F2203/45078 ,  H03F2203/45292 ,  H03F2203/45342

Abstract: PROBLEM TO BE SOLVED: To provide a method and device to expand a common mode range of a differential amplifier.
SOLUTION: A circuit includes a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit includes an input node to receive the common mode voltage and an output node to output a body voltage, and makes an inverse relation between the common mode voltage and the body voltage. The differential amplifier includes a pair of differences of transistors having a pair of body terminals coupled to the output node of the common mode voltage inversion circuit.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供扩展差分放大器的共模范围的方法和装置。 解决方案：电路包括共模检测电路，共模电压反相电路和差分放大器。 共模检测电路接收差分信号并检测共模电压。 共模电压反相电路耦合到共模检测电路。 共模电压反相电路包括用于接收共模电压的输入节点和用于输出体电压的输出节点，并且使共模电压与体电压成反比。 差分放大器包括具有耦合到共模电压反相电路的输出节点的一对主体端子的晶体管的一对差异。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：AT330362T

公开(公告)日：2006-07-15

申请号：AT02716131

申请日：2002-01-15

Applicant: IBM

Inventor： CRANFORD HAYDEN CLAVIE ,  GARVIN STACY JEAN ,  NORMAN VERNON ROBERTS ,  OWCZARSKI PAUL ALAN ,  SCHMATZ MARTIN LEO ,  STEVENS JOSEPH MARSH

IPC: H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H03L7/00

Abstract: The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.