公开(公告)号：DE3482747D1

公开(公告)日：1990-08-23

申请号：DE3482747

申请日：1984-10-16

Applicant: IBM

Inventor： CRANFORD JR ,  GARVIN STACY JEAN

IPC: H01L27/10 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H03K3/03 ,  H03K3/354 ,  H03K3/70

Abstract: A programmable oscillator (18) is provided for use on an integrated circuit chip. The oscillator (18) includes a plurality of inverted delay stages (80, 82, ...) connected in tandem between an input (INPUT) and an output node (Z). A single FET device (39) couples a common node (X) to a ground potential. Another FET device (31) controls the control node G. When a logic enabling signal is appropriately applied to the FET devices, the oscillator (18) is controlled so that internal nodes (G, H, ...) of the oscillator float high when it is off and no energy is dissipated. In addition, the ratio of delays between the delay stages (80, 82, ...) and the input stage (92) of the load (37) is such that the load (37) supplies the greater ratio of delays. This ensures that the oscillator's frequency of oscillation tracks the switching speed of the load (37).

公开(公告)号：DE3787080T2

公开(公告)日：1994-03-17

申请号：DE3787080

申请日：1987-10-31

Applicant: IBM

Inventor： CRANFORD HAYDEN CLAY ,  GARVIN STACY JEAN ,  HODGIN WENDY KAY ,  MULLEN JOHN MARK

IPC: H01L21/8247 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  H01L21/822 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H02M3/00 ,  H02M3/07 ,  H03K5/00

Abstract: On-chip multi-level voltage generating system comprising charge pump circuit means (26) responsive to a low voltage for supplying multiple voltages on a high voltage output, a plurality of selectable feedback paths connected to the output of said charge pump circuit means (26) with each feedback path controlling the charge pump circuit means to output a selected voltage level, and charge pump control means (28) coupled to a drive input (30) of the charge pump circuit means (26) and in series with each feedback path, and being responsive to enabling signals to activate the feedback path corresponding to the selected voltage level.

公开(公告)号：AT330362T

公开(公告)日：2006-07-15

申请号：AT02716131

申请日：2002-01-15

Applicant: IBM

Inventor： CRANFORD HAYDEN CLAVIE ,  GARVIN STACY JEAN ,  NORMAN VERNON ROBERTS ,  OWCZARSKI PAUL ALAN ,  SCHMATZ MARTIN LEO ,  STEVENS JOSEPH MARSH

IPC: H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H03L7/00

Abstract: The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

公开(公告)号：DE3787080D1

公开(公告)日：1993-09-23

申请号：DE3787080

申请日：1987-10-31

Applicant: IBM

Inventor： CRANFORD HAYDEN CLAY ,  GARVIN STACY JEAN ,  HODGIN WENDY KAY ,  MULLEN JOHN MARK

IPC: H01L21/8247 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  H01L21/822 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H02M3/00 ,  H02M3/07 ,  H03K5/00

Abstract: On-chip multi-level voltage generating system comprising charge pump circuit means (26) responsive to a low voltage for supplying multiple voltages on a high voltage output, a plurality of selectable feedback paths connected to the output of said charge pump circuit means (26) with each feedback path controlling the charge pump circuit means to output a selected voltage level, and charge pump control means (28) coupled to a drive input (30) of the charge pump circuit means (26) and in series with each feedback path, and being responsive to enabling signals to activate the feedback path corresponding to the selected voltage level.

公开(公告)号：DE3483880D1

公开(公告)日：1991-02-07

申请号：DE3483880

申请日：1984-10-16

Applicant: IBM

Inventor： CRANFORD JR ,  GARVIN STACY JEAN

IPC: H01L27/10 ,  G11C5/00 ,  G11C5/14 ,  G11C11/407 ,  G11C14/00 ,  G11C16/06 ,  G11C17/00 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07

Abstract: @ A voltage generating system provides a plurality of different voltages for powering a dynamic nonvolatile random access memory (NVRAM) chip. The voltage generating system includes a pair of charge pumps (28,48). Each charge pump is coupled to a controller (22, 44) that senses the voltage level at the output of the charge pump and generates an enabling signal when said voltage is at a predetermined value. The signal activates a power down circuit (34, 56) which adjusts the charge pump output to a desired voltage level. A programmable oscillator (18, 40) provides the clocking signals for the controller. The charge pumps and programmable oscillators are periodically deactivated by the controller. As a result, the overall power consumption of the chip is reduced.