公开(公告)号：JP2003346432A

公开(公告)日：2003-12-05

申请号：JP2002148290

申请日：2002-05-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： KATO KATSUHIKO ,  KURODA TAKASHI ,  UCHIIKE HIROSHI ,  TAKASE YASUHIRO

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/15

CPC classification number: G11B20/1833 ,  G11B2220/2516

Abstract: PROBLEM TO BE SOLVED: To attain the correction of a bigger error without increasing the overhead of a code.
SOLUTION: The correlation is generated among sectors 0-2 by making the exclusive OR (XOR) of user data (sector) 0, user data (sector) 1 and user data (sector) 2 to obtain virtual user data, and by producing C2 having the error correcting ability larger than that of C1 to the virtual user data, the error correction becomes available by C2 even though the error is uncorrectable (Uncorrectable) by C1.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：在不增加代码开销的情况下获得较大误差的校正。 解决方案：通过使用户数据（扇区）0，用户数据（扇区）1和用户数据（扇区）2的异或（XOR）0获得虚拟用户数据，在扇区0-2中生成相关性，以及 通过产生具有大于C1的纠错能力的C2到虚拟用户数据，即使错误是C1不可校正（不可校正），也可通过C2获得纠错。 版权所有（C）2004，JPO

公开(公告)号：JP2001101764A

公开(公告)日：2001-04-13

申请号：JP27412999

申请日：1999-09-28

Applicant: IBM

Inventor： TAKASE YASUHIRO ,  MURAKAMI MASAYUKI ,  KANAI TOSHIO

IPC: G06F1/32 ,  G06F1/04 ,  G11B19/00 ,  H03K17/22 ,  H03K19/003

Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of an electronic circuit to operate based on a clock signal when the power is applied. SOLUTION: The power consumption reduction circuit 40 is provided with a clock frequency reduction circuit 41. When a received POR signal is asserted, the clock frequency reduction circuit 41 decreases the frequency of a received CK signal and outputs the CK signal to an IC selection circuit 42. When the received POR is negated, the clock frequency reduction circuit 41 outputs the received CK signal to the IC selection circuit 42 as it is. The signal outputted from the clock frequency reduction circuit 41 is fed to a plurality of ICs 51, 52,..., IC 53 via the IC selection circuit 42.

公开(公告)号：JP2001282541A

公开(公告)日：2001-10-12

申请号：JP2000089860

申请日：2000-03-28

Applicant: IBM

Inventor： MURAKAMI MASAYUKI ,  TAKASE YASUHIRO ,  SAKAI TATSUYA

IPC: G06F3/06 ,  G06F9/445

Abstract: PROBLEM TO BE SOLVED: To easily change a microcode in a control element using a system LSI forming a DRAM in the same chip substrate without generating a production lead time and requiring the reevaluation of the LSI. SOLUTION: A semiconductor device 10 connecting its terminal 17 to an external serial ROM 11 is provided with a DRAM 14 formed on the same chip substrate, a comparator 20 for inputting data of one byte from the terminal 17 and comparing whether the data is 'FF' or '00' (both of which are hexadecimal numbers) or not and a selector 18 for selecting download from an internal serial mask ROM 19 when the compared result is true or selecting download from the external serial ROM 11 when the compared result is false. The downloaded program is recorded in the DRAM 14.