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公开(公告)号：US3622793A
公开(公告)日：1971-11-23
申请号：US3622793D
申请日：1969-03-28
Applicant: IBM
Inventor： DALTON JOHN J , TAYLOR GEORGE P
CPC classification number: G06K7/10831
Abstract: A light transmitting assembly utilizing fiber optic elements to pass light from a source to a sensing station. The assembly includes a mounting block or body for the fiber optic elements, having a single input channel adjacent the light source and plural output channels located adjacent the sensing station. The fiber optic elements are arranged in layers in the input channel, and each layer is randomly arranged in a separate output channel. Shadows cast on the input end of the fiber optic elements are diffused or averaged out over the layers, and a substantially equal amount of light emanates from each output channel.
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Patent Agency Ranking
公开(公告)号：CA1111922A
公开(公告)日：1981-11-03
申请号：CA292567
申请日：1977-12-07
Applicant: IBM
Inventor： AMES RICHARD N , HARDIN DICK K , LEININGER JOEL C , TAYLOR GEORGE P
Abstract: SYNCHRONOUS MICROCODE GENERATED INTERFACE FOR SYSTEM OF MICROCODED DATA PROCESSORS An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective mocrocodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
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公开(公告)号：CA951155A
公开(公告)日：1974-07-16
申请号：CA78212
申请日：1970-03-24
Applicant: IBM
Inventor： DALTON JOHN J , TAYLOR GEORGE P
IPC: G06K7/10
Abstract: 1289388 Light distributing assemblies INTERNATIONAL BUSINESS MACHINES CORP 16 Feb 1970 [28 March 1969] 7293/70 Heading G2J A light distributing assembly 10 comprises a light source 36 arranged in operation to illuminate an input window, such illumination being non- uniform having a zone of different intensity from the remainder of the window illumination, a plurality of fibre optic bundles, each bundle having an input and located in the input window and its output end in an individual output window, the input ends of the bundle being arranged so as to have equal proportions of their areas lying in said zone, and the fibres of each bundle being randomly distributed in the appropriate output window whereby illumination over each window is substantially uniform. The fibres in the input end of each bundle are arranged in horizontal layers when the light source is a lamp providing illumination with vertically extending dark zones, and the bundles are arranged in a mounting block 40 having an output face 42. The assembly 10 is used with a device 12 programmed to control a motor 20 of, for example, a key punch. When one of the holes 26 in a punched card 28 wound round a drum 14 corresponds with one of a plurality of holes 24 in a drum 14 and is aligned with a sensing device 38, the light from one of the output windows passes through the holes onto a corresponding photoresponsive element such as a photo-transistor in the sensing device 35. The arrangement of the fibres in the output window may be adapted to diffuse light from any non-uniform source, for example, by arranging the bundles of fibres radially to diffuse a circular dark zone of illumination. To manufacture the light distributing assembly, shims 61 Fig. 6 (not shown) used initially to separate the layers of fibres in the input window, are removed before the fibres are potted into the mounting block 40.
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公开(公告)号：FR2389175A1
公开(公告)日：1978-11-24
申请号：FR7809976
申请日：1978-03-28
Applicant: IBM
Inventor： AMES RICHARD N , HARDIN DICK K , LEININGER JOEL C , TAYLOR GEORGE P
Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
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公开(公告)号：FR2389173A1
公开(公告)日：1978-11-24
申请号：FR7809188
申请日：1978-03-23
Applicant: IBM
Inventor： LEININGER JOEL C , TAYLOR GEORGE P
Abstract: This carry save adder (CSA) utilizes a pair of edge-triggered flip-flops as output manifesting elements at each CSA bit position, one of these flip-flops being the "sum trigger" which registers the half-sum value (herein called the "sum bit"), and the other flip-flop of the pair being the "carry trigger" which registers the carry value resulting from the binary addition performed by the CSA at that bit position. Each trigger has a latch portion for storing a sum or carry bit value that can be set or changed only at the leading edge of a clock pulse, being stable in the period between clock pulses. A latched sum or carry output bit value at any CSA bit position can be re-entered at any time as input to the same bit position or another CSA bit position, depending upon the operation to be performed (add, left or right shift, or complement). Each trigger also produces an unlatched output sum or carry value known as a "presum" or "precarry" bit. These unlatched bit values may be utilized for trial or test purposes, such as inputs to a lookahead logic network for determining whether a proposed complemental subtraction in a division operation can or cannot be successfully performed.
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公开(公告)号：FR2389172A1
公开(公告)日：1978-11-24
申请号：FR7809181
申请日：1978-03-23
Applicant: IBM
Inventor： BIRNEY RICHARD E , LEININGER JOEL C , TAYLOR GEORGE P
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