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公开(公告)号：BR9202899A
公开(公告)日：1993-04-13
申请号：BR9202899
申请日：1992-07-28
Applicant: IBM
Inventor： AMES RICHARD N , MOORE VICTOR S
Abstract: Methods and apparatus are set forth which enable a data communications network (1) to perform decentralised uplink network control functions (decentralised away from the centralised general communications controller (GCC) level of the network hierarchy); (2) to minimise, or in some cases eliminate, the overhead expended in making power lever (signal strength) determinations and assessments at both the GCC and base station levels of the network hierarchy (for the purpose of managing uplink communications); and (3) to allow individual subscriber radios (terminals) to dynamically determine the most desirable base station to communicate with when exchanging information a host computer via a shared RF communication channel (the link between a terminal and the base station). Additionally, an illustrative radio frequency data communication network, built in accordance with the teachings of the invention as a modified version of an existing network, is described where the modified network incorporates the aforementioned methods and apparatus.
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公开(公告)号：FR2389175A1
公开(公告)日：1978-11-24
申请号：FR7809976
申请日：1978-03-28
Applicant: IBM
Inventor： AMES RICHARD N , HARDIN DICK K , LEININGER JOEL C , TAYLOR GEORGE P
Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
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公开(公告)号：CA2068009A1
公开(公告)日：1993-02-20
申请号：CA2068009
申请日：1992-05-05
Applicant: IBM
Inventor： AMES RICHARD N , MOORE VICTOR S
IPC: H04Q7/22 , H04B7/26 , H04L12/28 , H04Q7/28 , H04L12/56 , H04B7/185 , H04L12/52 , H04L5/16 , H04L12/48 , H04B7/10
Abstract: Methods and apparatus are set forth which enable a data communications network (1) to perform decentralised uplink network control functions (decentralised away from the centralised general communications controller (GCC) level of the network hierarchy); (2) to minimise, or in some cases eliminate, the overhead expended in making power lever (signal strength) determinations and assessments at both the GCC and base station levels of the network hierarchy (for the purpose of managing uplink communications); and (3) to allow individual subscriber radios (terminals) to dynamically determine the most desirable base station to communicate with when exchanging information a host computer via a shared RF communication channel (the link between a terminal and the base station). Additionally, an illustrative radio frequency data communication network, built in accordance with the teachings of the invention as a modified version of an existing network, is described where the modified network incorporates the aforementioned methods and apparatus.
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公开(公告)号：CA1111922A
公开(公告)日：1981-11-03
申请号：CA292567
申请日：1977-12-07
Applicant: IBM
Inventor： AMES RICHARD N , HARDIN DICK K , LEININGER JOEL C , TAYLOR GEORGE P
Abstract: SYNCHRONOUS MICROCODE GENERATED INTERFACE FOR SYSTEM OF MICROCODED DATA PROCESSORS An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective mocrocodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
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