公开(公告)号：CA1187189A

公开(公告)日：1985-05-14

申请号：CA426777

申请日：1983-04-27

Applicant: IBM

Inventor： MOORE VICTOR S ,  LEININGER JOEL C

IPC: G06F9/22 ,  H03K19/177 ,  G06F9/40

Abstract: BINARY LOGIC STRUCTURE EMPLOYING PROGRAMMABLE LOGIC ARRAYS AND USEFUL IN MICROWORD GENERATION APPARATUS Binary logic structure is described which requires less space on an integrated circuit chip. This structure includes an encode programmable logic array responsive to a first group of binary input signals for producing a smaller number of binary signals which are encoded to identify different binary value combinations for the first group of binary input signals. This structure further includes a decode programmable logic array responsive to a second group of binary input signals and to the encoded binary signals produced by the encode programmable logic array for producing binary output signals representing logical functions of binary input signals in both the first and second groups. The chip space occuppied by the encode programmable logic array is less than the additional chip space that would be required if the encode and decode programmable logic arrays were replaced by a single programmable logic array for receiving all the binary input signals in both the first and second groups. When used to provide microword generation apparatus for a microprogrammed digital system, the encode programmable logic array is responsive to a plural-bit system instruction for producing a plural-bit instruction identification signal uniquely representative of such system instruction but having a smaller number of bits than the system instruction. In such case, the decode programmable logic array is responsive to the instruction identification signal and to number signals produced by a sequence counter for producing a sequence of microwords needed to execute the system instruction.

公开(公告)号：FR2389175A1

公开(公告)日：1978-11-24

申请号：FR7809976

申请日：1978-03-28

Applicant: IBM

Inventor： AMES RICHARD N ,  HARDIN DICK K ,  LEININGER JOEL C ,  TAYLOR GEORGE P

IPC: G06F13/12 ,  G06F7/00 ,  G06F9/38 ,  G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06F13/00

Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.

公开(公告)号：CA1115849A

公开(公告)日：1982-01-05

申请号：CA325543

申请日：1979-04-11

Applicant: IBM

Inventor： FAIRCHILD PETER T ,  LEININGER JOEL C

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/305 ,  G06F9/318 ,  G06F9/34 ,  G06F9/355 ,  G06F12/06 ,  G06F9/06

Abstract: A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like. BC9-78-001

公开(公告)号：CA1111922A

公开(公告)日：1981-11-03

申请号：CA292567

申请日：1977-12-07

Applicant: IBM

Inventor： AMES RICHARD N ,  HARDIN DICK K ,  LEININGER JOEL C ,  TAYLOR GEORGE P

IPC: G06F13/12 ,  G06F7/00 ,  G06F9/38 ,  G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06F3/00

Abstract: SYNCHRONOUS MICROCODE GENERATED INTERFACE FOR SYSTEM OF MICROCODED DATA PROCESSORS An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective mocrocodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.

公开(公告)号：FR2389173A1

公开(公告)日：1978-11-24

申请号：FR7809188

申请日：1978-03-23

Applicant: IBM

Inventor： LEININGER JOEL C ,  TAYLOR GEORGE P

IPC: G06F7/505 ,  G06F7/483 ,  G06F7/50 ,  G06F7/508 ,  G06F7/509 ,  G06F7/53 ,  G06F7/385

Abstract: This carry save adder (CSA) utilizes a pair of edge-triggered flip-flops as output manifesting elements at each CSA bit position, one of these flip-flops being the "sum trigger" which registers the half-sum value (herein called the "sum bit"), and the other flip-flop of the pair being the "carry trigger" which registers the carry value resulting from the binary addition performed by the CSA at that bit position. Each trigger has a latch portion for storing a sum or carry bit value that can be set or changed only at the leading edge of a clock pulse, being stable in the period between clock pulses. A latched sum or carry output bit value at any CSA bit position can be re-entered at any time as input to the same bit position or another CSA bit position, depending upon the operation to be performed (add, left or right shift, or complement). Each trigger also produces an unlatched output sum or carry value known as a "presum" or "precarry" bit. These unlatched bit values may be utilized for trial or test purposes, such as inputs to a lookahead logic network for determining whether a proposed complemental subtraction in a division operation can or cannot be successfully performed.

公开(公告)号：FR2389172A1

公开(公告)日：1978-11-24

申请号：FR7809181

申请日：1978-03-23

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  LEININGER JOEL C ,  TAYLOR GEORGE P

IPC: G06F7/537 ,  G06F7/483 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/535 ,  G06F7/385