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    SOFT METAL CONDUCTOR AND FORMING METHOD THEREFOR
    3.
    发明专利
    SOFT METAL CONDUCTOR AND FORMING METHOD THEREFOR 审中-公开

    公开(公告)号：JP2004006768A

    公开(公告)日：2004-01-08

    申请号：JP2003091887

    申请日：2003-03-28

    Applicant: IBM

    Inventor： JOSHI RAJIV VASANT ,  TEJWANI MANU JAMNADAS

    IPC: H01L21/28 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/43

    Abstract: PROBLEM TO BE SOLVED: To provide a soft metal conductor where hardness on an uppermost surface without abrasion is improved after the surface is polished by a chemical mechanical polishing process. SOLUTION: The soft metal conductor 78 has an uppermost layer composed of particles having sufficiently large particle sizes so that the surface without abrasion is obtained after polishing in the chemical mechanical polishing step and the conductor is used for a semiconductor device. Metallic particles having the particle sizes of 200nm or above are bonded to the uppermost layer in a conductive soft metal structure. COPYRIGHT: (C)2004,JPO

    4.
    发明专利
    未知

    公开(公告)号：DE69529775D1

    公开(公告)日：2003-04-03

    申请号：DE69529775

    申请日：1995-07-05

    Applicant: IBM

    Inventor： JOSHI RAJIV VASANT ,  TEJWANI MANU JAMNADAS ,  SRIKRISHNAN KRIS VENKATRAMAN

    IPC: H01L21/28 ,  H01L21/203 ,  H01L21/205 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH4 gas followed by WF6 can be used to produce an in-situ hard cap of WxGey. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450 DEG C) without degrading the underlying metals.

    6.
    发明专利
    未知

    公开(公告)号：DE69529775T2

    公开(公告)日：2003-10-16

    申请号：DE69529775

    申请日：1995-07-05

    Applicant: IBM

    Inventor： JOSHI RAJIV VASANT ,  TEJWANI MANU JAMNADAS ,  SRIKRISHNAN KRIS VENKATRAMAN

    IPC: H01L21/28 ,  H01L21/203 ,  H01L21/205 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH4 gas followed by WF6 can be used to produce an in-situ hard cap of WxGey. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450 DEG C) without degrading the underlying metals.

    8.
    发明专利
    未知

    公开(公告)号：DE69513459T2

    公开(公告)日：2000-10-26

    申请号：DE69513459

    申请日：1995-07-05

    Applicant: IBM

    Inventor： JOSHI RAJIV VASANT ,  TEJWANI MANU JAMNADAS ,  SRIKRISHNAN KRIS VENKATRAMAN

    IPC: H01L21/28 ,  H01L21/203 ,  H01L21/205 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH4 gas followed by WF6 can be used to produce an in-situ hard cap of WxGey. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450 DEG C) without degrading the underlying metals.

    9.
    发明专利
    未知

    公开(公告)号：DE69513459D1

    公开(公告)日：1999-12-30

    申请号：DE69513459

    申请日：1995-07-05

    Applicant: IBM

    Inventor： JOSHI RAJIV VASANT ,  TEJWANI MANU JAMNADAS ,  SRIKRISHNAN KRIS VENKATRAMAN

    IPC: H01L21/28 ,  H01L21/203 ,  H01L21/205 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH4 gas followed by WF6 can be used to produce an in-situ hard cap of WxGey. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450 DEG C) without degrading the underlying metals.

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