公开(公告)号：JPH1050943A

公开(公告)日：1998-02-20

申请号：JP12686997

申请日：1997-05-16

Applicant: IBM

Inventor： GOLDEN KEVIN M ,  PAN PAI-HUNG ,  STEWART KEVIN J ,  THOMAS ALAN C

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To get a trench capacitor, which has buried plates in high integration density, by a simple method, by including a stage of etching a diffusion source, according to the nonexposed section of resist, and a stage of completing a trench capacitor. SOLUTION: A trench 210 is etched within a substrate 110, according to a TEOS layer 140 made by pattern. Then in order to fill up the trench 210 surely, resist is made poor in temperature stability so that the reflow of the resist may be executed at high temperature after adhesion. Next, the resist is provided with a recess as far as about 1.5 micron below the substrate by exposure and development. Then, the trench is filled up with n+ polycrystalline silicon or other proper material. Next, using reactive ion etching, the filler is lowered to about 1.2μm from the surface of the substrate. The residual part of the trench is fill up again with n+ polycrystalline silicon or other proper material, and it is slightly lowered by RIE or other proper etching method, whereupon it is completed.

公开(公告)号：WO0163648A3

公开(公告)日：2002-04-18

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定用于期望的电熔丝的图案，其中该图案包括除了熔丝部分的局部变窄的区域之外基本恒定宽度的熔丝部分 在此电熔丝被设计为吹塑。 该方法然后包括提供光刻掩模衬底并且在光刻掩模衬底上产生适于吸收能量束的透射的熔丝掩模元件。 熔丝掩模元件具有基本恒定宽度的第一掩模部分和与熔丝部分的局部缩窄区域对应的第二掩模部分，第一掩模部分对应于基本恒定宽度的期望电熔丝图案部分。 第二掩模部分包括与第一掩模部分隔开的另外的掩模元件，变窄的宽度部分或第一掩模部分中的间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的配置，该电图案包括保险丝部分的局部变窄的区域，在电熔丝被设计成在该区域处被吹过，在通过能量束通过光刻掩模并且到 抗蚀剂层。 优选地，在所确定的熔丝图案上具有基本恒定宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：WO0163648A9

公开(公告)日：2002-10-24

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定所需电熔丝的图案，其中所述图案包括基本恒定宽度的熔丝部分，除了熔丝部分的局部变窄区域 电熔丝被设计在其上。 该方法然后包括提供光刻掩模基板，并在光刻掩模基板上产生适于吸收能量束透射的熔丝屏蔽元件。 熔丝掩模元件具有对应于基本恒定宽度的期望电熔丝图案部分的基本恒定宽度的第一掩模部分和对应于熔丝部分的局部变窄区域的第二掩模部分。 第二掩模部分包括与第一掩模部分间隔开的附加掩模元件，第一掩模部分中的窄宽度部分或间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的构造，包括将电熔丝设计成熔断部分的熔断部分的局部变窄区域，以使能量束通过光刻掩模并进入 抗蚀剂层。 优选地，确定的熔丝图案上的基本上恒定的宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：DE102004016704B4

公开(公告)日：2007-08-16

申请号：DE102004016704

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： THOMAS ALAN C ,  PREUNINGER JUERGEN ,  BUTT SHAHID ,  KUNKEL GERHARD

IPC: G03F7/20 ,  G03B27/32 ,  G03B27/42 ,  G03B27/52 ,  G03F7/207

Abstract: A projected image is formed during a material substrate. A photolithographic mask is illuminated with substantially coherent light at an oblique angle of incidence with respect to a surface of the photolithographic mask. The photolithographic mask includes a substantially transparent mask substrate and one or more lines and spaces patterns formed on the mask substrate and having a periodicity P. The mask substrate includes at least one phase shifting region. At least part of the light that is transmitted through the photolithographic mask is collected using one or more projection lenses which project the portion of the transmitted light onto the material substrate. The material substrate is disposed substantially parallel with, but at a distance from, a focal plane of the projection lens system. The phase shifting region of the mask substrate and the distance from the focal plane are selected such that a substantially focused image is projected onto the material substrate that includes the lines and spaces patterned but with a periodicity P/2.