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    TRAINING OF ARTIFICIAL NEURAL NETWORKS
    2.
    发明专利
    TRAINING OF ARTIFICIAL NEURAL NETWORKS 未知

    公开(公告)号：CA3137231A1

    公开(公告)日：2020-11-19

    申请号：CA3137231

    申请日：2020-05-12

    Applicant: IBM

    Inventor： LE GALLO-BOURDEAU MANUEL ,  KHADDAM-ALJAMEH RIDUAN ,  KULL LUKAS ,  FRANCESE PIER ANDREA ,  TOIFL THOMAS ,  SEBASTIAN ABU ,  ELEFTHERIOU EVANGELOS STAVROS

    IPC: G06N3/063 ,  G06N3/08

    Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n = 1 and (p + n + m) = N where m = 0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

    TRAINING OF ARTIFICIAL NEURAL NETWORKS
    5.
    发明专利
    TRAINING OF ARTIFICIAL NEURAL NETWORKS 未知

    公开(公告)号：SG11202110345XA

    公开(公告)日：2021-10-28

    申请号：SG11202110345X

    申请日：2020-05-12

    Applicant: IBM

    Inventor： LE GALLO-BOURDEAU MANUEL ,  KHADDAM-ALJAMEH RIDUAN ,  KULL LUKAS ,  FRANCESE PIER ANDREA ,  TOIFL THOMAS ,  SEBASTIAN ABU ,  ELEFTHERIOU EVANGELOS STAVROS

    IPC: G06N3/063 ,  G06N3/08

    Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n≥1 and (p+n+m)=N where m≥0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

    Clock recovery method and apparatus
    6.
    发明专利
    Clock recovery method and apparatus 未知

    公开(公告)号：GB2521526A

    公开(公告)日：2015-06-24

    申请号：GB201420722

    申请日：2014-11-21

    Applicant: IBM

    Inventor： TOIFL THOMAS ,  KULL LUKAS ,  FRANCESE PIER ANDREA

    IPC: H04L7/033

    Abstract: A method of phase rotation for use in clock recovery comprises the steps of: i) providing a timing estimation value (TEV) at least indicating for each of the input data symbols f(t) whether an input data sample has been sampled early or late by a sampling clock signal CLK; ii) generating a phase offset value φn-k indicating a phase rotation PR of the sampling clock signal CLK based on the TEV; and iii) modifying the timing function value based on a change of the phase offset value Δφ, resulting in the timing estimation value (TEV). In an embodiment, the timing estimation means includes a timing function block 61 which receives the corrected data samples and applies a Mueller-Muller timing function. An inner loop feeds back the obtained phase offset value φn-k to an adder 62 to correct the delay caused by propagation of the incoming data stream the ADC 2 and the optional feed forward equaliser 5. In general, the outer control loop and the inner control loop both perform feedback control to keep the timing function value to zero.

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