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    System and method for floating point unit with feedback prior to normalization and rounding
    1.
    发明专利
    System and method for floating point unit with feedback prior to normalization and rounding 有权
    用于在正态化和圆形之前使用反馈浮点单元的系统和方法

    公开(公告)号：JP2006221622A

    公开(公告)日：2006-08-24

    申请号：JP2006016958

    申请日：2006-01-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FLEISCHER BRUCE M ,  HAESS JUERGEN ,  KROENER MICHAEL ,  MARTIN S SHUMUUKURAA ,  SCHWARZ ERIC M ,  DAO-TRONG SON

    IPC: G06F7/76

    CPC classification number: G06F7/483 ,  G06F7/499 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/5443 ,  G06F2207/382

    Abstract: PROBLEM TO BE SOLVED: To improve performance of a floating point unit which performs feedback prior to normalization or rounding. SOLUTION: This system is for performing floating point arithmetic operation including an input register adapted for receiving an operand. This system further includes a mechanism for performing shifting or masking operation in response to determination that the operand is a un-normalization format. The system further includes an instruction for performing single-precision increment of the operand in response to determination that the operand is single-precision, that the operand requires the incrementing based on the result of previous operation and that the previous operation has not performed the incrementing. The operand is created in the previous operation. The system further includes an instruction for performing double precision incrementing of the operand in response to determination that the operand is double precision, that the operand requires the incrementing based on the result of the previous operation and that the previous operation has not performed the incrementing. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提高在归一化或舍入之前执行反馈的浮点单元的性能。

    解决方案：该系统用于执行浮点运算，包括适于接收操作数的输入寄存器。 该系统还包括用于响应于操作数是非归一化格式的确定而执行移位或掩蔽操作的机制。 该系统还包括响应于确定操作数是单精度来执行操作数的单精度增量的指令，操作数基于先前操作的结果需要增加，并且先前的操作没有执行递增 。 操作数是在上一操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。 版权所有（C）2006，JPO＆NCIPI

    Residue calculation in modulo system using 4:2 counter
    5.
    发明专利
    Residue calculation in modulo system using 4:2 counter 未知

    公开(公告)号：GB2456406A

    公开(公告)日：2009-07-22

    申请号：GB0822762

    申请日：2008-12-15

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  FLEISCHER BRUCE MARTIN ,  HAESS JUERGEN ,  TRONG SON DAO ,  SCHWARZ ERIC MARK ,  WETTER HOLGER

    IPC: G06F7/72

    Abstract: A residue of an operand with a width of n bits with respect to a modulo m where m=2b-1, can be calculated by partitioning the operand into segments, each of b bits starting with the Least Significant Bit (LSB). The segments are applied to a counter reduction tree (21) comprising levels (22, 23) of adders (24) The adders (24) of a first level (22) below an operand register (25) with successive registers keeping the successive bit positions of the operand are 4:2 counters (24) having four inputs (In1, In2, In3, In4) plus a propagate input (44), a carry and a sum output (45, 46) plus a propagate output (43) each. the first level (22) are grouped in fours, such that the propagate outputs (43) are ring like connected with the propagate inputs (44), and that the first to fourth inputs (In1, In2, In3, In4) of the counters (24) are connected with successive registers of said operand register (25) such that first inputs (In4) of the counters (24) are connected with four successive registers in ascending order followed by second (In3), third (In2) and fourth inputs (In1), wherein a decoding is performed only one time at the end of the counter tree (21) and thus at the end of the residue generation process. This leads to a reduction in the area needed on the chip to make the calculation, relaxes the timing requirement, as the calculation requires fewer logical levels, and increases the error detection rate for a single random type of operation.

    Method for executing a load instruction in a pipeline processor, putting the data in the target address into a buffer then loading the requested data.
    6.
    发明专利
    Method for executing a load instruction in a pipeline processor, putting the data in the target address into a buffer then loading the requested data. 未知

    公开(公告)号：GB2454816A

    公开(公告)日：2009-05-20

    申请号：GB0822115

    申请日：2008-12-04

    Applicant: IBM

    Inventor： TRONG SON DAO ,  HAESS JUERGEN ,  HUTTON DAVID SHANE ,  KLEIN MICHAEL ,  RELL JOHN GILBERT JR ,  SCHWARZ ERIC MARK ,  SHUM KEVIN CHUNG-LUNG

    IPC: G06F9/312 ,  G06F9/38

    Abstract: Disclosed is a method and system for operating the execution unit of a computer, the execution unit having a pipeline-based execution flow during which load instructions are processed. The load instructions having the function of loading data from a storage means into a predetermined location within the pipeline, preferably a register-implemented pipeline. The method has the steps of, when a load instruction occurs in the pipeline, reading (610) the current value of the target location, and buffering (620) the current target value at a predetermined location within said pipeline. Next, the value of the source location is loaded (610) and stored (620) at the target location, the pipeline is executed according to its execution flow, using the loaded value for computing purposes. If an event (630) indicating that the loaded value is not correct occurs, (660) the buffered original value may be used instead of the loaded value. The execution unit may be a floating point unit with the reading and/or loading of the data being done using a multiply-add data path.

    Checking Arithmetic operations using residue modulo generation by applying the modulo operations of the prime factors of the checking value.
    9.
    发明专利
    Checking Arithmetic operations using residue modulo generation by applying the modulo operations of the prime factors of the checking value. 未知

    公开(公告)号：GB2456624A

    公开(公告)日：2009-07-22

    申请号：GB0822772

    申请日：2008-12-15

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  KROENER KLAUS MICHAEL ,  HAESS JUERGEN

    IPC: G06F11/00 ,  G06F7/72 ,  G06F11/10

    Abstract: Disclosed is a method and an apparatus using residue modulo checking for arithmetic operations. To get a high Modulo m and thus a high residue modulo checking coverage within a checking flow 31, at least two modulo operations 32, 33 are separately applied in parallel, a first Modulo q0 operation and at least one second Modulo qn operation, where q0, q1, q2,... qn-1, qn, are different primes with m=q0*q1*q2*. . .*qn-1*qn. The checking is done by comparing the residue modulo of the result of an arithmetic operation 36 with the results of the modulo operations on the inputs of the arithmetic operation 35. The modulo operations may be provided by a modulo decode for the modulos applied in the parallel flows or by providing a modulo shift table. The values of m may be 15 or 255 and the values of q may be 3 and 5 or 3, 5 and 17, respectfully.

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