公开(公告)号：JPH08236688A

公开(公告)日：1996-09-13

申请号：JP31661995

申请日：1995-12-05

Applicant: IBM

Inventor： KENESU EDOWAADO BIIRUSUTEIN JI ,  KUROODO RUISU BAATEIN ,  JIYON EDOWAADO KURONIN ,  UEIN JIYON HAUERU ,  JIEIMUSU MAAKU RIISU ,  ROBAATO BAADO FUIRITSUPUSU

IPC: H01L23/538 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide the manufacturing method of an electronic module with a side face and end face metallization layer which are electrically interconnected. SOLUTION: A stack with plural switched IC chips is provided. A side-face thin film metallization layer 43 is formed on this stack. Next, a tip-face thin film metallization layer 33 is formed on the stack and the side-face and tip-face thin film metallization layers are electrically and directly interconnected. This method also includes the process of forming the long stack of the IC chip, testing the chip of the stack and segmenting the long stack into many small stacks based on the result of the test.

公开(公告)号：JPH09106968A

公开(公告)日：1997-04-22

申请号：JP17785096

申请日：1996-07-08

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN ,  UEIN JIYON HAUERU ,  HAWAADO REO KARUTAA ,  PATORISHIA EREN MARUMIRION ,  ANSONII MAIKERU PARAGONIA ,  BAANADETSUTO AN PIASON ,  DENISU AASAA SHIYUMITSUTO

IPC: H01L21/304 ,  H01L21/301 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065

Abstract: PROBLEM TO BE SOLVED: To demarcate the edge of an IC chip accurately at water-level manufacturing by forming first trenches into a wafer by lithography, polishing the main plane of the IC chip towards the bottom sections of the first trenches and thinning the IC chip. SOLUTION: First trenches 25 crossing the first main plane of a water 11 and having bottom sections are formed into the wafer 11 by lithography. The second main plane of an IC chip is polished towards the bottoms of the first trenches 25 and towards the first main plane of the wafer 11 so that the first trenches 25 demarcate at least one edge of the IC chip, and the IC chip is thinned. The first trenches 25 are filled with an insulation material 35, a transfer metallic layer 39 is formed onto the first main plane of the wafer, and second trenches 45 coinciding with the first trenches 25 are formed, and the layer 39 is polished.

公开(公告)号：JPH0883881A

公开(公告)日：1996-03-26

申请号：JP10511594

申请日：1994-05-19

Applicant: IBM

Inventor： KUROODO RUISU BAATEIN ,  POORU OORUDEN FUARAA SHINIA ,  UEIN JIYON HAUERU ,  KURISUTOFUAA POORU MIRAA ,  DEEBUITSUDO JIEIKOBU PAARUMAN

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

Abstract: PURPOSE: To provide a three-dimensional packaging of stacked semiconductor device chips, which increases the operating speed of a device, enhances the reliability of a package, enhances the adaptability of the package to the already- existing semiconductor device processing technique and is made using an insulating material and an adhesive material. CONSTITUTION: A metal transfer layer 9 is adhered to the surfaces of six passivated chips and all electrical contacts are assembled 14 at the edge part common to the chips. The layer 9 is made to be separated from the surfaces of the chips and the adjacent chips in a stack of the chips by a polymer layer 10, which is low in dielectric constant and has a thermal expansion coefficient matching that of the stacked chips. Adhesion layers 11A and 11 are adhered to the chips and the chips are partially cured at a wafer level and thereafter, when the chips are stacked to form a three-dimensionally stacked material, the chips are completely cured, whereby a coupling of a first polymer layer with the adjacent chips in the stack is reinforced.

公开(公告)号：JPH0845871A

公开(公告)日：1996-02-16

申请号：JP13017395

申请日：1995-05-29

Applicant: IBM

Inventor： KUROODO RUI BERUTAN ,  UEIN JIYON HAUERU ,  KENESU EDOWAADO BAIRUSHIYUTAIN

IPC: H01L21/28 ,  H01L21/98 ,  H01L25/065

Abstract: PURPOSE: To simultaneously form metal coating on a plurality of electronic modules by using a work piece corresponding to selected side surfaces of a plurality of electronic modules on the same plane between adjacent stacked electronic modules, and cutting a metal coating pattern in a region on a plane different from the side surfaces. CONSTITUTION: A work piece 12 is completed with temporary adhesive 24 on an exposed surface of a separation material layer 22. A plurality of semiconductor chips 10 are deposited such that a flat main surface of each chip is opposite to that of adjacent chip. A long stack structure 28 extends horizontally or vertically, including a plurality of work pieces 12 each between two adjacent semiconductor chips 10. Next, the separation material layer 22 is removed from selected side surfaces of the stack structure to form grooves 32 in the long stack structure, to eliminate side-surface interruption regions from the work pieces. Next, the selected side surfaces of the long stack structure are coated with metal coating 34. The metal coating is automatically interrupted in the grooves 32 of the work pieces.

公开(公告)号：JPH07183453A

公开(公告)日：1995-07-21

申请号：JP21690794

申请日：1994-09-12

Applicant: IBM

Inventor： KUROODO RUI BARUTAN ,  UEIN JIYON HAUERU ,  ERITSUKU RII HETSUDOBAAGU ,  HAWAADO REO KARUTAA ,  GOODON AASAA KERII JIYUNIA

IPC: H01L25/18 ,  G11C5/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11

Abstract: PURPOSE: To reduce the dimensions as compared with standard regulations of business by emulating a next generation memory chip through the use of an easily available existing generation memory chip. CONSTITUTION: A memory subunit 12 comprising N memory chips each having M memory devices 14 is formed. A control logic chip 22 controls external communication of the N memory chips such that a single memory chip architecture having N×M memory devices appears at the I/O pin 24 of a module. The memory chips constituting the subunit are interconnected electrically with the control logic chip using a previously formed electric interface layer 18 at one end of the memory subunit. The control logic chip has smaller dimensions than the memory chip constituting the subunit. A lead frame 32 having an inner through opening is secured to the electric interface layer.