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公开(公告)号：JPS54112173A
公开(公告)日：1979-09-01
申请号：JP78479
申请日：1979-01-10
Applicant: IBM
IPC: H01L21/027 , H01J37/21 , H01J37/304
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公开(公告)号：DE3169257D1
公开(公告)日：1985-04-18
申请号：DE3169257
申请日：1981-08-28
Applicant: IBM
Inventor： MAUER IV , MICHAIL MICHEL SALIB , WOODARD OLLIE CLIFTON
IPC: H01L21/027 , H01J37/147 , H01J37/317 , H01J37/30
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公开(公告)号：MY117872A
公开(公告)日：2004-08-30
申请号：MYPI9705546
申请日：1997-11-19
Applicant: IBM
Abstract: A PROCESSOR(34) WHICH OPTIMIZES PERFORMANCE OPPORTUNISTICALLY BY USING A HIERARCHY OF VARIABLES COMPRISING VOLTAGE, CLOCKING AND THE OPERATIONS BEING PERFORMED BY THE PROCESSOR OR ITS SYSTEM. THE INVENTION ACCOMPLISHES PERFORMANCE OPTIMIZATION BY DEFINING VARIOUS STATES WITH THE GOAL THAT THE PROCESSOR STAYS IN AN OPTIMAL PERFORMANCE STATE OF ACCELERATED VOLTAGE AND CLOCK WHEN THE PROCESSOR EXECUTIONAL UNITS ARE OPERATING. THE STATES ARE SELECTED BY A LOGIC NETWORK(36) BASED ON INFORMATION THAT IS PROVIDED BY TEMPERATURE SENSORS AND A PERFORMANCE CONTROL(32). THE LOGIC NETWORK CAN BE ENVISIONED AS AN UP-DOWN COUNTER. THE COUNTER CAN BE ADVANCED UP OR DOWN THE STATE "LADDER" AS THE CONDITIONS WARRANT. (FIG. 2)
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公开(公告)号：DE3879466D1
公开(公告)日：1993-04-22
申请号：DE3879466
申请日：1988-12-06
Applicant: IBM
Inventor： MICHAIL MICHEL SALIB , WALSH JAMES LEO
IPC: H03K19/00 , H03K19/082 , H03K19/086 , H03K17/16
Abstract: A half current switch comprising: at least one input transistor (16), a load resistance (42, 44) connected between a first voltage reference and the collector of the input transistor, a constant-current resistance (32) connected between the emitter of the input transistor and a second voltage reference, and a feedback means including at least one feedback connected to the constant-current resistance. The feedback means further includes means for biasing the feedback transistor (36) to drive a current through the constant current resistance (32) which, when flowing, increases with an increasing main current and decreases with a decreasing main current through the input transistor. The feedback means thus causes a constant current to be drawn by the input transistor (16) when it is conducting, thereby controlling the capacitance of the input transistor while maintaining the output level constant. In a preferred embodiment, the feedback means comprises a PNP transistor with its base connected t the collector of the input transistor, with its emitter connected to the first voltage reference, and with its collector connected to the emitter of the input transistor. The PNP transistor not only acts as a feedback device to control current, but also acts to prevent oscillations when a speed-up capacitor (54) is used in the circuit.
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公开(公告)号：GB2320994B
公开(公告)日：2001-07-11
申请号：GB9726216
申请日：1997-12-12
Applicant: IBM
Inventor： GOODNOW KENNETH JOSEPH , MICHAIL MICHEL SALIB , PRICER WILBUR DAVID , VENTRONE SEBASTIAN THEODORE
Abstract: A calibrated multi-voltage level system is disclosed having a network of devices, including a first and a second device. The first device comprises a processor for generating data, an encoding unit for encoding the data into a first data signal having multiple voltage levels, and a transmitting unit for transmitting the encoded data signal to the second device. The first device also comprises a calibration unit for sending a first calibration signal to the second device, and for storing a second calibration signal from the second device; and an adaptation unit for correcting the second data signal from the second device with the stored second calibration signal.
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Patent Agency Ranking
公开(公告)号：DE2962859D1
公开(公告)日：1982-07-08
申请号：DE2962859
申请日：1979-01-24
Applicant: IBM
IPC: H01L21/027 , H01J37/21 , H01J37/304
Abstract: A method and apparatus for applying focus correction to an E-beam or charged particle system to compensate for wafer warp and mask tilt. In an electron beam system including a registration system which measures the position of four registration marks with the beam and calculates the apparent magnification error of a given chip, means are also provided for using magnification and rotation error information to calculate a height error factor and to apply a compensating current to a dynamic focusing coil of the electron beam to move the effective beam focal plane to a position which matches the wafer or mask plane at each chip site.
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公开(公告)号：DE69019585T2
公开(公告)日：1996-01-18
申请号：DE69019585
申请日：1990-02-20
Applicant: IBM
Inventor： CAVALIERE JOHN RICHARD , CHAN ALAN KA-JUN , MICHAIL MICHEL SALIB
IPC: G11C8/16 , G11C11/411 , G11C8/00
Abstract: A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; sensing means connected to each of the base-collector terminals in the transistor pair, each of the sensing means including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connect-ed to the word line, and (c) means connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; writing means connected to each of the transistors in the transistor pair, the writing means including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and means for supplying constant current to each of the base-collector terminals and to each of the commonly connected anodes of the first and second diodes. The memory cell permits read access or select while maintaining the voltages on the latch nodes stable.
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公开(公告)号：DE69019585D1
公开(公告)日：1995-06-29
申请号：DE69019585
申请日：1990-02-20
Applicant: IBM
Inventor： CAVALIERE JOHN RICHARD , CHAN ALAN KA-JUN , MICHAIL MICHEL SALIB
IPC: G11C8/16 , G11C11/411 , G11C8/00
Abstract: A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; sensing means connected to each of the base-collector terminals in the transistor pair, each of the sensing means including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connect-ed to the word line, and (c) means connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; writing means connected to each of the transistors in the transistor pair, the writing means including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and means for supplying constant current to each of the base-collector terminals and to each of the commonly connected anodes of the first and second diodes. The memory cell permits read access or select while maintaining the voltages on the latch nodes stable.
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公开(公告)号：MY133334A
公开(公告)日：2007-11-30
申请号：MYPI0304490
申请日：1997-11-19
Applicant: IBM
Abstract: A PROCESSOR (34) WHICH OPTIMIZES PERFORMANCE OPPORTUNISTICALLY BY USING A HIERARCHY OF VARIABLES COMPRISING VOLTAGE, CLOCKING AND THE OPERATIONS BEING PERFORMED BY THE PROCESSOR OR ITS SYSTEM.THE INVENTION ACCOMPLISHES PERFORMANCE OPTIMIZATION BY DEFINING VARIOUS STATES WITH THE GOAL THAT THE PROCESSOR STAYS IN AN OPTIMAL PERFORMANCE STATE OF ACCELERATED VOLTAGE AND CLOCK WHEN THE PROCESSOR EXECUTIONAL UNITS ARE OPERATING.THE STATES ARE SELECTED BY A LOGIC NETWORK (36) BASED ON INFORMATION THAT IS PROVIDED BY TEMPERATURE SENSORS AND A PERFORMANCE CONTROL (32). THE LOGIC NETWORK CAN BE ENVISIONED AS AN UP-DOWN COUNTER.THE COUNTER CAN BE ADVANCED UP OR DOWN THE STATE "LADDER" AS THE CONDITIONS WARRANT.(FIG 2)
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公开(公告)号：SG66414A1
公开(公告)日：1999-07-20
申请号：SG1997004113
申请日：1997-11-21
Applicant: IBM
Abstract: A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.
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