公开(公告)号：BR8006769A

公开(公告)日：1981-04-28

申请号：BR8006769

申请日：1980-10-21

Applicant: IBM

Inventor： VOGL N JR ,  HARROUN T ,  HELLER L

IPC: G11C27/04 ,  G11C19/28 ,  H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  G11C11/40

Abstract: An SPS Serial-Parallel-Serial charge coupled device (CCD) memory system is provided wherein a single tap, preferably a storage node, on an input serial or shift register (10) is connected to the input of a plurality of parallel shift registers (14) through a fan out circuit (D) and the output of the plurality of parallel shift registers is connected to a single tap, preferably a storage node, on an output serial or shift register (12) through a fan in circuit (E).

公开(公告)号：CA939076A

公开(公告)日：1973-12-25

申请号：CA100736

申请日：1970-12-16

Applicant: IBM

Inventor： ORDEMANN F JR ,  BEAUSOLEIL W ,  PRICER W ,  VOGL N JR

IPC: G06F3/08 ,  G11C7/00 ,  G11C11/00